//Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp
// Spec Reference: ldimmhalf dreg lo
# mach: bfin

.include "testutils.inc"
	start



INIT_R_REGS -1;

// test Dreg
R0.L = 0x0001;
R1.L = 0x0003;
R2.L = 0x0005;
R3.L = 0x0007;
R4.L = 0x0009;
R5.L = 0x000b;
R6.L = 0x000d;
R7.L = 0x000f;
CHECKREG r0, 0xFFFF0001;
CHECKREG r1, 0xFFFF0003;
CHECKREG r2, 0xFFFF0005;
CHECKREG r3, 0xFFFF0007;
CHECKREG r4, 0xFFFF0009;
CHECKREG r5, 0xFFFF000b;
CHECKREG r6, 0xFFFF000D;
CHECKREG r7, 0xFFFF000F;

R0.L = 0x0020;
R1.L = 0x0040;
R2.L = 0x0060;
R3.L = 0x0080;
R4.L = 0x00a0;
R5.L = 0x00b0;
R6.L = 0x00c0;
R7.L = 0x00d0;
CHECKREG r0, 0xFFFF0020;
CHECKREG r1, 0xFFFF0040;
CHECKREG r2, 0xFFFF0060;
CHECKREG r3, 0xFFFF0080;
CHECKREG r4, 0xFFFF00a0;
CHECKREG r5, 0xFFFF00b0;
CHECKREG r6, 0xFFFF00c0;
CHECKREG r7, 0xFFFF00d0;

R0.L = 0x0100;
R1.L = 0x0200;
R2.L = 0x0300;
R3.L = 0x0400;
R4.L = 0x0500;
R5.L = 0x0600;
R6.L = 0x0700;
R7.L = 0x0800;
CHECKREG r0, 0xFFFF0100;
CHECKREG r1, 0xFFFF0200;
CHECKREG r2, 0xFFFF0300;
CHECKREG r3, 0xFFFF0400;
CHECKREG r4, 0xFFFF0500;
CHECKREG r5, 0xFFFF0600;
CHECKREG r6, 0xFFFF0700;
CHECKREG r7, 0xFFFF0800;

R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
R0.L = 0x7fff;
R1.L = 0x7ffe;
R2.L = -32768;
R3.L = -32767;
R4.L = 32767;
R5.L = 32766;
R6.L = 32765;
R7.L = 32764;
CHECKREG r0, 0x00007fff;
CHECKREG r1, 0x00007ffe;
CHECKREG r2, 0x00008000;
CHECKREG r3, 0x00008001;
CHECKREG r4, 0x00007FFF;
CHECKREG r5, 0x00007FFE;
CHECKREG r6, 0x00007FFD;
CHECKREG r7, 0x00007FFC;

pass
