/*
 * Autogenerated by $Id: IEMAllCImplA64SysRegsAndIns-armv8.cpp $
 * from the open source v9Ap6-A specs, build 406 (5e0a212688c6bd7aee92394b6f5e491b4d0fee1d)
 * dated Sun Dec 15 22:18:44 2024 UTC.
 *
 * Do not edit!
 */

/*
 * Copyright (C) 2025 Oracle and/or its affiliates.
 *
 * This file is part of VirtualBox base platform packages, as
 * available from https://www.virtualbox.org.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation, in version 3 of the
 * License.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <https://www.gnu.org/licenses>.
 *
 * SPDX-License-Identifier: GPL-3.0-only
 */


#define LOG_GROUP LOG_GROUP_IEM_CIMPL
#define VMCPU_INCL_CPUM_GST_CTX
#include "IEMInternal.h"
#include <VBox/vmm/vm.h>
#include "VBox/err.h"

#include "iprt/armv8.h"

#include "IEMMc.h"
#include "IEMInline-armv8.h"





/*
 * A64.MRS
 *
 *  615 registers
 *  507 complete - 297 with unresolved registers
 *   67 incomplete
 *
 * Warnings:
 *   Assignment from Identifier: Unable to map AArch64.ICV_BPR0_EL1 to anything
 *   Assignment from Identifier: Unable to map AArch64.ICV_BPR1_EL1 to anything
 *   Assignment from Identifier: Unable to map AArch64.ICV_CTLR_EL1 to anything (2 times)
 *   Assignment from Identifier: Unable to map AArch64.ICV_HPPIR0_EL1 to anything
 *   Assignment from Identifier: Unable to map AArch64.ICV_HPPIR1_EL1 to anything
 *   Assignment from Identifier: Unable to map AArch64.ICV_IAR0_EL1 to anything
 *   Assignment from Identifier: Unable to map AArch64.ICV_IAR1_EL1 to anything
 *   Assignment from Identifier: Unable to map AArch64.ICV_IGRPEN0_EL1 to anything
 *   Assignment from Identifier: Unable to map AArch64.ICV_IGRPEN1_EL1 to anything
 *   Assignment from Identifier: Unable to map AArch64.ICV_NMIAR1_EL1 to anything
 *   Assignment from Identifier: Unable to map AArch64.ICV_PMR_EL1 to anything (2 times)
 *   Assignment from Identifier: Unable to map AArch64.ICV_RPR_EL1 to anything (2 times)
 *   Assignment/Identifier: No CPUMCTX mapping for register AArch64.CNTHV_CVAL_EL2 (3 times)
 *   Assignment/Identifier: No CPUMCTX mapping for register AArch64.RCWMASK_EL1 (2 times)
 *   Assignment/Identifier: No CPUMCTX mapping for register AArch64.RCWSMASK_EL1
 *   Call to untranslated function: CNTHCTL_EL2_VHE
 *   Call to untranslated function: ConstrainUnpredictableProcedure (6 times)
 *   Call to untranslated function: EffectivePMSCR_EL2_EE
 *   Call to untranslated function: EffectiveTRFCR_EL2_EE (2 times)
 *   Call to untranslated function: GetNumEventCountersAccessible (4 times)
 *   Call to untranslated function: GetNumEventCountersSelfHosted (2 times)
 *   Call to untranslated function: UInt (98 times)
 *   Call to untranslated function: UnimplementedIDRegister (3 times)
 *   Call to untranslated function: ZeroExtend (3 times)
 *   Generic field: Field "AMCNTEN0" not found in register "HAFGRTR_EL2" (2 times)
 *   Generic field: Field "AMCNTEN1" not found in register "HAFGRTR_EL2" (2 times)
 *   Generic field: Field "F0" not found in register "PMUACR_EL1" (2 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.CNTHV_CTL_EL2 (looking up field ENABLE) (3 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICC_SRE_EL1 (looking up field SRE) (12 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICC_SRE_EL2 (looking up field Enable)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICC_SRE_EL2 (looking up field SRE) (18 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICH_HCR_EL2 (looking up field TALL0) (4 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICH_HCR_EL2 (looking up field TALL1) (5 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICH_HCR_EL2 (looking up field TC) (3 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAM2_EL2 (looking up field EnMPAMSM)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAM2_EL2 (looking up field TIDR)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAM2_EL2 (looking up field TRAPMPAM0EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAM2_EL2 (looking up field TRAPMPAM1EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMBW2_EL2 (looking up field nTRAP_MPAMBW0_EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMBW2_EL2 (looking up field nTRAP_MPAMBW1_EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMBW2_EL2 (looking up field nTRAP_MPAMBWIDR_EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMBW2_EL2 (looking up field nTRAP_MPAMBWSM_EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMHCR_EL2 (looking up field TRAP_MPAMIDR_EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMIDR_EL1 (looking up field HAS_HCR) (12 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMIDR_EL1 (looking up field HAS_TIDR)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMIDR_EL1 (looking up field VPMR_MAX) (7 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.PMSELR_EL0 (looking up field SEL) (22 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.SPMSELR_EL0 (looking up field SYSPMUSEL) (69 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.TRFCR_EL1 (looking up field EE)
 */


/**
 * OSDTRRX_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_OSDTRRX_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,0,2), "OSDTRRX_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,0,2), "OSDTRRX_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG))
    //     X<t,0x40> = OSDTRRX_EL1;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = OSDTRRX_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = OSDTRRX_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = OSDTRRX_EL1;
}


/**
 * MDCCINT_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MDCCINT_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.MDccInt.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.MDccInt.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG))
    //     X<t,0x40> = MDCCINT_EL1;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDCCINT_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDCCINT_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MDCCINT_EL1;
}


/**
 * MDSCR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MDSCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x158, puDst);
        *puDst = pVCpu->cpum.GstCtx.Mdscr.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Mdscr.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.MDSCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x158>;
    //     else
    //         X<t,0x40> = MDSCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDSCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MDSCR_EL1;
}


/**
 * OSDTRTX_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_OSDTRTX_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,3,2), "OSDTRTX_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,3,2), "OSDTRTX_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG))
    //     X<t,0x40> = OSDTRTX_EL1;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = OSDTRTX_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = OSDTRTX_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = OSDTRTX_EL1;
}


/**
 * MDSELR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MDSELR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fDebugV8p9)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,4,2), "MDSELR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,4,2), "MDSELR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_Debugv8p9))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EBWE == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nMDSELR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EBWE == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDSELR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EBWE == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EBWE == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDSELR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MDSELR_EL1;
}


/**
 * MDSTEPOP_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0101', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MDSTEPOP_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fStep2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,5,2), "MDSTEPOP_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,5,2), "MDSTEPOP_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_STEP2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnSTEPOP == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nMDSTEPOP_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnSTEPOP == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDSTEPOP_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnSTEPOP == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnSTEPOP == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDSTEPOP_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MDSTEPOP_EL1;
}


/**
 * OSECCR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0110', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_OSECCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (!(pVCpu->cpum.GstCtx.fOsLck & UINT32_C(1)/*OSLK*/))
            *puDst = 0;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,6,2),
                                         "OSECCR_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (!(pVCpu->cpum.GstCtx.fOsLck & UINT32_C(1)/*OSLK*/))
            *puDst = 0;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,6,2),
                                         "OSECCR_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.OSECCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.OSLSR_EL1.OSLK == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = OSECCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.OSLSR_EL1.OSLK == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = OSECCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.OSLSR_EL1.OSLK == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = OSECCR_EL1;
}


/**
 * MDRAR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MDRAR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x900) /*TDE,TDRA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,0,0), "MDRAR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,0,0), "MDRAR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDRA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDRAR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDRAR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MDRAR_EL1;
}


/**
 * OSLSR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0001', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_OSLSR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x500) /*TDE,TDOSA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,1,4), "OSLSR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,1,4), "OSLSR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDOSA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.OSLSR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDOSA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDOSA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = OSLSR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDOSA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDOSA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = OSLSR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = OSLSR_EL1;
}


/**
 * OSDLR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0001', 'CRm': '0011', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_OSDLR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x500) /*TDE,TDOSA*/) && pGstFeats->fDoubleLock)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,3,4), "OSDLR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,3,4), "OSDLR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && AArch64.MDCR_EL3.TDOSA == '1'
    //         && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_DoubleLock)
    //              && AArch64.HDFGRTR_EL2.OSDLR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDOSA) != '00'
    //              && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL2.TDOSA")))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && AArch64.MDCR_EL3.TDOSA == '1'
    //              && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = OSDLR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && AArch64.MDCR_EL3.TDOSA == '1'
    //         && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && AArch64.MDCR_EL3.TDOSA == '1'
    //              && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = OSDLR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = OSDLR_EL1;
}


/**
 * DBGPRCR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DBGPRCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x500) /*TDE,TDOSA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,4,4), "DBGPRCR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,4,4), "DBGPRCR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDOSA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.DBGPRCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDOSA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDOSA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = DBGPRCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDOSA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDOSA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = DBGPRCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = DBGPRCR_EL1;
}


/**
 * PMCCNTSVR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1110', 'CRm': '1011', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMCCNTSVR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3Ss)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,14,11,7), "PMCCNTSVR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3_SS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSS == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMSSDATA == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCCNTSVR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCCNTSVR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMCCNTSVR_EL1;
}


/**
 * PMICNTSVR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1110', 'CRm': '1100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMICNTSVR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3Icntr || !pGstFeats->fPmuV3Ss)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,14,12,0), "PMICNTSVR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_PMUv3_ICNTR) && IsFeatureImplemented(FEAT_PMUv3_SS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSS == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMSSDATA == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMICNTSVR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMICNTSVR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMICNTSVR_EL1;
}


/**
 * DBGAUTHSTATUS_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0111', 'CRm': '1110', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DBGAUTHSTATUS_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,14,6),
                                     "DBGAUTHSTATUS_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu,
                                 ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,14,6),
                                 "DBGAUTHSTATUS_EL1",
                                 puDst,
                                 uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.DBGAUTHSTATUS_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = DBGAUTHSTATUS_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = DBGAUTHSTATUS_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = DBGAUTHSTATUS_EL1;
}


/**
 * DBGCLAIMSET_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0111', 'CRm': '1000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DBGCLAIMSET_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,8,6),
                                     "DBGCLAIMSET_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,8,6), "DBGCLAIMSET_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.DBGCLAIM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = DBGCLAIMSET_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = DBGCLAIMSET_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = DBGCLAIMSET_EL1;
}


/**
 * DBGCLAIMCLR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0111', 'CRm': '1001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DBGCLAIMCLR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,9,6),
                                     "DBGCLAIMCLR_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,9,6), "DBGCLAIMCLR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.DBGCLAIM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = DBGCLAIMCLR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = DBGCLAIMCLR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = DBGCLAIMCLR_EL1;
}


/**
 * SPMACCESSR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1001', 'CRm': '1101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMACCESSR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x8e8, puDst);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,3),
                                     "SPMACCESSR_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,13,3),
                                     "SPMACCESSR_EL2",
                                     puDst,
                                     uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,3), "SPMACCESSR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMACCESSR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x8e8>;
    //     else
    //         X<t,0x40> = SPMACCESSR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = SPMACCESSR_EL2;
    //     else
    //         X<t,0x40> = SPMACCESSR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMACCESSR_EL1;
}


/**
 * SPMIIDR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1001', 'CRm': '1101', 'op2': '100'})
 * Transformation status: 15 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMIIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMIIDR_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else
        *puDst = SPMIIDR_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMID == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMIIDR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMIIDR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMIIDR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * SPMDEVARCH_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1001', 'CRm': '1101', 'op2': '101'})
 * Transformation status: 15 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMDEVARCH_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMDEVARCH_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else
        *puDst = SPMDEVARCH_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMID == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMDEVARCH_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMDEVARCH_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMDEVARCH_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * SPMDEVAFF_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1001', 'CRm': '1101', 'op2': '110'})
 * Transformation status: 15 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMDEVAFF_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMDEVAFF_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else
        *puDst = SPMDEVAFF_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMDEVAFF_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMDEVAFF_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMDEVAFF_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMDEVAFF_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * SPMCFGR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1001', 'CRm': '1101', 'op2': '111'})
 * Transformation status: 15 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMCFGR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMCFGR_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else
        *puDst = SPMCFGR_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMID == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMCFGR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMCFGR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMCFGR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * SPMINTENSET_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '001'})
 * Transformation status: 15 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMINTENSET_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMINTENSET_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else
        *puDst = SPMINTENSET_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMINTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMINTENSET_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMINTENSET_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMINTENSET_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * SPMINTENCLR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '010'})
 * Transformation status: 15 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMINTENCLR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMINTENCLR_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else
        *puDst = SPMINTENCLR_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMINTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMINTENCLR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMINTENCLR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMINTENCLR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * TRCTRACEIDR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCTRACEIDR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,1), "TRCTRACEIDR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,1), "TRCTRACEIDR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCTRACEIDR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCTRACEIDR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCTRACEIDR;
}


/**
 * TRCVICTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCVICTLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,2), "TRCVICTLR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,2), "TRCVICTLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCVICTLR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVICTLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVICTLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVICTLR;
}


/**
 * TRCIDR8 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR8(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,6));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,6));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR8;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR8;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR8;
}


/**
 * TRCIMSPEC0 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIMSPEC0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,7), "TRCIMSPEC0", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,7), "TRCIMSPEC0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCIMSPECn == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIMSPEC0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIMSPEC0;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIMSPEC0;
}


/**
 * TRCPRGCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCPRGCTLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,0), "TRCPRGCTLR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,0), "TRCPRGCTLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCPRGCTLR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCPRGCTLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCPRGCTLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCPRGCTLR;
}


/**
 * TRCQCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCQCTLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,7)) >> 14) & UINT32_C(1)/*QFILT*/) != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,1), "TRCQCTLR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,1), "TRCQCTLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR0.QFILT == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCQCTLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCQCTLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCQCTLR;
}


/**
 * TRCVIIECTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCVIIECTLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || (iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) & UINT32_C(0xf)/*NUMACPAIRS*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,2), "TRCVIIECTLR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,2), "TRCVIIECTLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && UInt(AArch64.TRCIDR4.NUMACPAIRS) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVIIECTLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVIIECTLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVIIECTLR;
}


/**
 * TRCIDR9 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR9(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,6));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,6));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR9;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR9;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR9;
}


/**
 * TRCRSR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCRSR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,0), "TRCRSR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,0), "TRCRSR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCRSR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCRSR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCRSR;
}


/**
 * TRCIDR2 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1010', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,7));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,7));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR2;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR2;
}


/**
 * TRCSTALLCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCSTALLCTLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,11,7)) >> 26) & UINT32_C(1)/*STALLCTL*/) != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,11,0),
                                     "TRCSTALLCTLR",
                                     puDst,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,11,0), "TRCSTALLCTLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR3.STALLCTL == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSTALLCTLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSTALLCTLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSTALLCTLR;
}


/**
 * TRCIDR3 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1011', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR3(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,11,7));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,11,7));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR3;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR3;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR3;
}


/**
 * TRCTSCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCTSCTLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || !(iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,7)) & UINT32_C(0x1f000000)/*TSSIZE*/))
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,0), "TRCTSCTLR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,0), "TRCTSCTLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR0.TSSIZE != '00000'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCTSCTLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCTSCTLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCTSCTLR;
}


/**
 * TRCIDR4 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR4(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR4;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR4;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR4;
}


/**
 * TRCSYNCPR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCSYNCPR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,0), "TRCSYNCPR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,0), "TRCSYNCPR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSYNCPR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSYNCPR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSYNCPR;
}


/**
 * TRCIDR5 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1101', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR5(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,7));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,7));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR5;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR5;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR5;
}


/**
 * TRCCCCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCCCCTLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,7)) >>  7) & UINT32_C(1)/*TRCCCI*/) != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,14,0), "TRCCCCTLR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,14,0), "TRCCCCTLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR0.TRCCCI == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCCCTLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCCCTLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCCCTLR;
}


/**
 * TRCIDR6 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR6(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,14,7));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,14,7));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR6;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR6;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR6;
}


/**
 * TRCBBCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCBBCTLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,7)) >>  5) & UINT32_C(1)/*TRCBB*/) != 1
        || (iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) & UINT32_C(0xf)/*NUMACPAIRS*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,15,0), "TRCBBCTLR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,15,0), "TRCBBCTLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(   IsFeatureImplemented(FEAT_ETE)
    //     && IsFeatureImplemented(FEAT_TRC_SR)
    //     && AArch64.TRCIDR0.TRCBB == '1'
    //     && UInt(AArch64.TRCIDR4.NUMACPAIRS) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCBBCTLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCBBCTLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCBBCTLR;
}


/**
 * TRCIDR7 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1111', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR7(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,15,7));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,15,7));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR7;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR7;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR7;
}


/**
 * TRCITEEDCR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCITEEDCR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr || !pGstFeats->fIte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,1), "TRCITEEDCR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,1), "TRCITEEDCR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && IsFeatureImplemented(FEAT_ITE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCITEEDCR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCITEEDCR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCITEEDCR;
}


/**
 * TRCVISSCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCVISSCTLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || (iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) & UINT32_C(0xf)/*NUMACPAIRS*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,2), "TRCVISSCTLR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,2), "TRCVISSCTLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && UInt(AArch64.TRCIDR4.NUMACPAIRS) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVISSCTLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVISSCTLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVISSCTLR;
}


/**
 * TRCIDR10 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR10(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,6));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,6));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR10;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR10;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR10;
}


/**
 * TRCSTATR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCSTATR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,0), "TRCSTATR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,0), "TRCSTATR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCSTATR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSTATR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSTATR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSTATR;
}


/**
 * TRCVIPCSSCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCVIPCSSCTLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) >> 12) & UINT32_C(0xf)/*NUMPC*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,2),
                                     "TRCVIPCSSCTLR",
                                     puDst,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,2), "TRCVIPCSSCTLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && UInt(AArch64.TRCIDR4.NUMPC) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVIPCSSCTLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVIPCSSCTLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVIPCSSCTLR;
}


/**
 * TRCIDR11 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0011', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR11(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,6));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,6));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR11;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR11;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR11;
}


/**
 * TRCCONFIGR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCCONFIGR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,4,0), "TRCCONFIGR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,4,0), "TRCCONFIGR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCONFIGR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCONFIGR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCONFIGR;
}


/**
 * TRCIDR12 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0100', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,4,6));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,4,6));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR12;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR12;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR12;
}


/**
 * TRCIDR13 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0101', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR13(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,5,6));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,5,6));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR13;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR13;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR13;
}


/**
 * TRCAUXCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCAUXCTLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,0), "TRCAUXCTLR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,0), "TRCAUXCTLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCAUXCTLR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCAUXCTLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCAUXCTLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCAUXCTLR;
}


/**
 * TRCSEQRSTEVR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0110', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCSEQRSTEVR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || !(iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,7)) & UINT32_C(0xe000000)/*NUMSEQSTATE*/))
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,4), "TRCSEQRSTEVR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,4), "TRCSEQRSTEVR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR5.NUMSEQSTATE != '000'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSEQRSTEVR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSEQRSTEVR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSEQRSTEVR;
}


/**
 * TRCSEQSTR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0111', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCSEQSTR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || !(iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,7)) & UINT32_C(0xe000000)/*NUMSEQSTATE*/))
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,7,4), "TRCSEQSTR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,7,4), "TRCSEQSTR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR5.NUMSEQSTATE != '000'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCSEQSTR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSEQSTR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSEQSTR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCSEQSTR;
}


/**
 * TRCEVENTCTL0R - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCEVENTCTL0R(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || !(iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) & UINT32_C(0xf0000)/*NUMRSPAIR*/))
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,0),
                                     "TRCEVENTCTL0R",
                                     puDst,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,0), "TRCEVENTCTL0R", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR4.NUMRSPAIR != '0000'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCEVENTCTL0R;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCEVENTCTL0R;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCEVENTCTL0R;
}


/**
 * TRCIDR0 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,7));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,7));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR0;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR0;
}


/**
 * TRCEVENTCTL1R - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCEVENTCTL1R(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,9,0),
                                     "TRCEVENTCTL1R",
                                     puDst,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,9,0), "TRCEVENTCTL1R", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCEVENTCTL1R;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCEVENTCTL1R;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCEVENTCTL1R;
}


/**
 * TRCIDR1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1001', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCIDR1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,9,7));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,9,7));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCIDR1;
}


/**
 * TRCOSLSR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0001', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCOSLSR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,1,1,4), "TRCOSLSR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,1,1,4), "TRCOSLSR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCOSLSR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCOSLSR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCOSLSR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCOSLSR;
}


/**
 * TRCCIDCCTLR0 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCCIDCCTLR0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) >> 24) & UINT32_C(0xf)/*NUMCIDC*/) <= 0
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,7)) >>  5) & UINT32_C(0x1f)/*CIDSIZE*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,0,2), "TRCCIDCCTLR0", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,0,2), "TRCCIDCCTLR0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(   IsFeatureImplemented(FEAT_ETE)
    //     && IsFeatureImplemented(FEAT_TRC_SR)
    //     && UInt(AArch64.TRCIDR4.NUMCIDC) > 0
    //     && UInt(AArch64.TRCIDR2.CIDSIZE) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCIDCCTLR0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCIDCCTLR0;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCIDCCTLR0;
}


/**
 * TRCCIDCCTLR1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCCIDCCTLR1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) >> 24) & UINT32_C(0xf)/*NUMCIDC*/) <= 4
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,7)) >>  5) & UINT32_C(0x1f)/*CIDSIZE*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,1,2), "TRCCIDCCTLR1", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,1,2), "TRCCIDCCTLR1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(   IsFeatureImplemented(FEAT_ETE)
    //     && IsFeatureImplemented(FEAT_TRC_SR)
    //     && UInt(AArch64.TRCIDR4.NUMCIDC) > 4
    //     && UInt(AArch64.TRCIDR2.CIDSIZE) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCIDCCTLR1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCIDCCTLR1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCIDCCTLR1;
}


/**
 * TRCVMIDCCTLR0 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCVMIDCCTLR0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) >> 28) & UINT32_C(0xf)/*NUMVMIDC*/) <= 0
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,7)) >> 10) & UINT32_C(0x1f)/*VMIDSIZE*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,2,2),
                                     "TRCVMIDCCTLR0",
                                     puDst,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,2,2), "TRCVMIDCCTLR0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(   IsFeatureImplemented(FEAT_ETE)
    //     && IsFeatureImplemented(FEAT_TRC_SR)
    //     && UInt(AArch64.TRCIDR4.NUMVMIDC) > 0
    //     && UInt(AArch64.TRCIDR2.VMIDSIZE) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVMIDCCTLR0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVMIDCCTLR0;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVMIDCCTLR0;
}


/**
 * TRCVMIDCCTLR1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCVMIDCCTLR1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) >> 28) & UINT32_C(0xf)/*NUMVMIDC*/) <= 4
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,7)) >> 10) & UINT32_C(0x1f)/*VMIDSIZE*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,3,2),
                                     "TRCVMIDCCTLR1",
                                     puDst,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,3,2), "TRCVMIDCCTLR1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(   IsFeatureImplemented(FEAT_ETE)
    //     && IsFeatureImplemented(FEAT_TRC_SR)
    //     && UInt(AArch64.TRCIDR4.NUMVMIDC) > 4
    //     && UInt(AArch64.TRCIDR2.VMIDSIZE) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVMIDCCTLR1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVMIDCCTLR1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCVMIDCCTLR1;
}


/**
 * TRCAUTHSTATUS - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0111', 'CRm': '1110', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCAUTHSTATUS(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,14,6),
                                     "TRCAUTHSTATUS",
                                     puDst,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,14,6), "TRCAUTHSTATUS", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCAUTHSTATUS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCAUTHSTATUS;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCAUTHSTATUS;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCAUTHSTATUS;
}


/**
 * TRCDEVARCH - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0111', 'CRm': '1111', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCDEVARCH(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,15,6));
    }
    else
    {
        if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,15,6));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCDEVARCH;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCDEVARCH;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCDEVARCH;
}


/**
 * TRCDEVID - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0111', 'CRm': '0010', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCDEVID(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,2,7), "TRCDEVID", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,2,7), "TRCDEVID", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCID == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCDEVID;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCDEVID;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCDEVID;
}


/**
 * TRCCLAIMSET - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0111', 'CRm': '1000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCCLAIMSET(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,8,6), "TRCCLAIMSET", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,8,6), "TRCCLAIMSET", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCCLAIM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCLAIMSET;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCLAIMSET;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCLAIMSET;
}


/**
 * TRCCLAIMCLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0111', 'CRm': '1001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCCLAIMCLR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,9,6), "TRCCLAIMCLR", puDst, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,9,6), "TRCCLAIMCLR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRCCLAIM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCLAIMCLR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCLAIMCLR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRCCLAIMCLR;
}


/**
 * BRBCR_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_BRBCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x8e0, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,0), "BRBCR_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,0,0), "BRBCR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,0), "BRBCR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.nBRBCTL == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x8e0>;
    //     else
    //         X<t,0x40> = BRBCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = BRBCR_EL2;
    //     else
    //         X<t,0x40> = BRBCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = BRBCR_EL1;
}


/**
 * BRBFCR_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_BRBFCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,1), "BRBFCR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,1), "BRBFCR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.nBRBCTL == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBFCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBFCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = BRBFCR_EL1;
}


/**
 * BRBTS_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_BRBTS_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,2), "BRBTS_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,2), "BRBTS_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.nBRBDATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBTS_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBTS_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = BRBTS_EL1;
}


/**
 * BRBINFINJ_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_BRBINFINJ_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,0),
                                     "BRBINFINJ_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,0), "BRBINFINJ_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.nBRBDATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBINFINJ_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBINFINJ_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = BRBINFINJ_EL1;
}


/**
 * BRBSRCINJ_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_BRBSRCINJ_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,1),
                                     "BRBSRCINJ_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,1), "BRBSRCINJ_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.nBRBDATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBSRCINJ_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBSRCINJ_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = BRBSRCINJ_EL1;
}


/**
 * BRBTGTINJ_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_BRBTGTINJ_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,2),
                                     "BRBTGTINJ_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,2), "BRBTGTINJ_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.nBRBDATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBTGTINJ_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBTGTINJ_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = BRBTGTINJ_EL1;
}


/**
 * BRBIDR0_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_BRBIDR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,2,0), "BRBIDR0_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,2,0), "BRBIDR0_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.nBRBIDR == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBIDR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBIDR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = BRBIDR0_EL1;
}


/**
 * MDCCSR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '0000', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MDCCSR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_32(12)/*TDCC*/)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
                || (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/)))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,0,1,0), "MDCCSR_EL0", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,0,1,0), "MDCCSR_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,0,1,0), "MDCCSR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG))
    //     X<t,0x40> = MDCCSR_EL0;
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.TDCC == '1')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.HCR_EL2.TGE == '1' || (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDCCSR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDCCSR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDCCSR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MDCCSR_EL0;
}


/**
 * DBGDTR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '0000', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DBGDTR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_32(12)/*TDCC*/)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
                || (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/)))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpReadDbgDtrEl0U64(pVCpu, puDst);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpReadDbgDtrEl0U64(pVCpu, puDst);
    }
    return iemCImplHlpReadDbgDtrEl0U64(pVCpu, puDst);
    /* -------- Original code specification: -------- */
    // if (Halted())
    //     X<t,0x40> = Read_DBGDTR_EL0(0x40);
    // else if (PSTATE.EL == EL0)
    //     if (AArch64.MDSCR_EL1.TDCC == '1')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.HCR_EL2.TGE == '1' || (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = Read_DBGDTR_EL0(0x40);
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = Read_DBGDTR_EL0(0x40);
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = Read_DBGDTR_EL0(0x40);
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = Read_DBGDTR_EL0(0x40);
}


/**
 * DBGDTRRX_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '0000', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DBGDTRRX_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_32(12)/*TDCC*/)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
                || (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/)))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpReadDbgDtrEl0U32(pVCpu, puDst);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpReadDbgDtrEl0U32(pVCpu, puDst);
    }
    return iemCImplHlpReadDbgDtrEl0U32(pVCpu, puDst);
    /* -------- Original code specification: -------- */
    // if (Halted())
    //     X<t,0x20> = Read_DBGDTR_EL0(0x20);
    // else if (PSTATE.EL == EL0)
    //     if (AArch64.MDSCR_EL1.TDCC == '1')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.HCR_EL2.TGE == '1' || (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x20> = Read_DBGDTR_EL0(0x20);
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x20> = Read_DBGDTR_EL0(0x20);
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x20> = Read_DBGDTR_EL0(0x20);
    // else if (PSTATE.EL == EL3)
    //     X<t,0x20> = Read_DBGDTR_EL0(0x20);
}


/**
 * SPMCR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '000'})
 * Transformation status: 33 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMCR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMCR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMCR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else
        *puDst = SPMCR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   !ELIsInHost(EL0)
    //              &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMCR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMCR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMCR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMCR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMCR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMCR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * SPMCNTENSET_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '001'})
 * Transformation status: 33 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMCNTENSET_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMCNTENSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMCNTENSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else
        *puDst = SPMCNTENSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   !ELIsInHost(EL0)
    //              &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMCNTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMCNTENSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMCNTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMCNTENSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMCNTENSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMCNTENSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * SPMCNTENCLR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '010'})
 * Transformation status: 33 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMCNTENCLR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMCNTENCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMCNTENCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else
        *puDst = SPMCNTENCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   !ELIsInHost(EL0)
    //              &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMCNTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMCNTENCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMCNTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMCNTENCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMCNTENCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMCNTENCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * SPMOVSCLR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '011'})
 * Transformation status: 33 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMOVSCLR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMOVSCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMOVSCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else
        *puDst = SPMOVSCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   !ELIsInHost(EL0)
    //              &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMOVS == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMOVSCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMOVS == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMOVSCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMOVSCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMOVSCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * SPMSELR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMSELR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,5), "SPMSELR_EL0", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,5), "SPMSELR_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,5), "SPMSELR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMSELR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMSELR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMSELR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMSELR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMSELR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMSELR_EL0;
}


/**
 * SPMOVSSET_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1110', 'op2': '011'})
 * Transformation status: 33 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMOVSSET_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMOVSSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = SPMOVSSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    }
    else
        *puDst = SPMOVSSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   !ELIsInHost(EL0)
    //              &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMOVS == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMOVSSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMOVS == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMOVSSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMOVSSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMOVSSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * DBGVCR32_EL2 - OrderedDict({'op0': '10', 'op1': '100', 'CRn': '0000', 'CRm': '0111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DBGVCR32_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAa32El1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,0,7,0), "DBGVCR32_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = DBGVCR32_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = DBGVCR32_EL2;
}


/**
 * BRBCR_EL2 - OrderedDict({'op0': '10', 'op1': '100', 'CRn': '1001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_BRBCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,0,0), "BRBCR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = BRBCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = BRBCR_EL2;
}


/**
 * SPMACCESSR_EL2 - OrderedDict({'op0': '10', 'op1': '100', 'CRn': '1001', 'CRm': '1101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMACCESSR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,13,3), "SPMACCESSR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMACCESSR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMACCESSR_EL2;
}


/**
 * BRBCR_EL12 - OrderedDict({'op0': '10', 'op1': '101', 'CRn': '1001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_BRBCR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x8e0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,0), "BRBCR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x8e0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = BRBCR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = BRBCR_EL1;
    //     else
    //         Undefined()
}


/**
 * SPMACCESSR_EL12 - OrderedDict({'op0': '10', 'op1': '101', 'CRn': '1001', 'CRm': '1101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMACCESSR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x8e8, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,3),
                                     "SPMACCESSR_EL1",
                                     puDst,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x8e8>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = SPMACCESSR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SPMACCESSR_EL1;
    //     else
    //         Undefined()
}


/**
 * SPMACCESSR_EL3 - OrderedDict({'op0': '10', 'op1': '110', 'CRn': '1001', 'CRm': '1101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMACCESSR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMACCESSR_EL3;
}


/**
 * SPMROOTCR_EL3 - OrderedDict({'op0': '10', 'op1': '110', 'CRn': '1001', 'CRm': '1110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMROOTCR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_RME) && IsFeatureImplemented(FEAT_SPMU)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMROOTCR_EL3<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * SPMSCR_EL1 - OrderedDict({'op0': '10', 'op1': '111', 'CRn': '1001', 'CRm': '1110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPMSCR_EL1(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveELUsingSecurityState(EL1, true) && IsFeatureImplemented(FEAT_SPMU)))
    //     Undefined()
    // else if (IsCurrentSecurityState(SS_NonSecure) || (IsFeatureImplemented(FEAT_RME) && IsCurrentSecurityState(SS_Realm)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMSCR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMSCR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SPMSCR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPMSCR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)>;
}


/**
 * MIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            *puDst = pVCpu->cpum.GstCtx.VPidrEl2.u64;
        else
            *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,0,0));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,0,0));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGRTR_EL2.MIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled())
    //         X<t,0x40> = VPIDR_EL2;
    //     else
    //         X<t,0x40> = MIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = MIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MIDR_EL1;
}


/**
 * MPIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            *puDst = pVCpu->cpum.GstCtx.VMpidrEl2.u64;
        else
            *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,0,5));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,0,5));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGRTR_EL2.MPIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled())
    //         X<t,0x40> = VMPIDR_EL2;
    //     else
    //         X<t,0x40> = MPIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = MPIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPIDR_EL1;
}


/**
 * REVIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_REVIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(16)/*TID1*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,0,6));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,0,6));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TID1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.REVIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = REVIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = REVIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = REVIDR_EL1;
}


/**
 * ID_PFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_PFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,0));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,0));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_PFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_PFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_PFR0_EL1;
}


/**
 * ID_PFR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_PFR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,1));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,1));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_PFR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_PFR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_PFR1_EL1;
}


/**
 * ID_DFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_DFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,2));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,2));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_DFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_DFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_DFR0_EL1;
}


/**
 * ID_AFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,3));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,3));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AFR0_EL1;
}


/**
 * ID_MMFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_MMFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,4));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,4));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_MMFR0_EL1;
}


/**
 * ID_MMFR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_MMFR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,5));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,5));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_MMFR1_EL1;
}


/**
 * ID_MMFR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_MMFR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,6));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,6));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_MMFR2_EL1;
}


/**
 * ID_MMFR3_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0001', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_MMFR3_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,7));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,7));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR3_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR3_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_MMFR3_EL1;
}


/**
 * ID_ISAR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_ISAR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,0));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,0));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_ISAR0_EL1;
}


/**
 * ID_ISAR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_ISAR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,1));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,1));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_ISAR1_EL1;
}


/**
 * ID_ISAR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_ISAR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,2));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,2));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_ISAR2_EL1;
}


/**
 * ID_ISAR3_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_ISAR3_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,3));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,3));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR3_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR3_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_ISAR3_EL1;
}


/**
 * ID_ISAR4_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_ISAR4_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,4));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,4));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR4_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR4_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_ISAR4_EL1;
}


/**
 * ID_ISAR5_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_ISAR5_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,5));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,5));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR5_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR5_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_ISAR5_EL1;
}


/**
 * ID_MMFR4_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_MMFR4_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,6));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,6));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_MMFR4_EL1)
    //                  || ImpDefBool("ID_MMFR4_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR4_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR4_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_MMFR4_EL1;
}


/**
 * ID_ISAR6_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_ISAR6_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,7));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,7));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_ISAR6_EL1)
    //                  || ImpDefBool("ID_ISAR6_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR6_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_ISAR6_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_ISAR6_EL1;
}


/**
 * MVFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MVFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,0));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,0));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MVFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MVFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MVFR0_EL1;
}


/**
 * MVFR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MVFR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,1));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,1));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MVFR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MVFR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MVFR1_EL1;
}


/**
 * MVFR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MVFR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,2));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,2));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MVFR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MVFR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MVFR2_EL1;
}


/**
 * ID_PFR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0011', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_PFR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,4));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,4));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_PFR2_EL1)
    //                  || ImpDefBool("ID_PFR2_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_PFR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_PFR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_PFR2_EL1;
}


/**
 * ID_DFR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_DFR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,5));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,5));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_DFR1_EL1)
    //                  || ImpDefBool("ID_DFR1_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_DFR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_DFR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_DFR1_EL1;
}


/**
 * ID_MMFR5_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0011', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_MMFR5_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,6));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,6));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_MMFR5_EL1)
    //                  || ImpDefBool("ID_MMFR5_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR5_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_MMFR5_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_MMFR5_EL1;
}


/**
 * ID_AA64PFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64PFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,0));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,0));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64PFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64PFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64PFR0_EL1;
}


/**
 * ID_AA64PFR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64PFR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,1));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,1));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64PFR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64PFR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64PFR1_EL1;
}


/**
 * ID_AA64PFR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64PFR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,2));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,2));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_AA64PFR2_EL1)
    //                  || ImpDefBool("ID_AA64PFR2_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64PFR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64PFR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64PFR2_EL1;
}


/**
 * ID_AA64ZFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64ZFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,4));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,4));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_AA64ZFR0_EL1)
    //                  || ImpDefBool("ID_AA64ZFR0_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64ZFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64ZFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64ZFR0_EL1;
}


/**
 * ID_AA64SMFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64SMFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,5));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,5));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_AA64SMFR0_EL1)
    //                  || ImpDefBool("ID_AA64SMFR0_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64SMFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64SMFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64SMFR0_EL1;
}


/**
 * ID_AA64FPFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64FPFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,7));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,7));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_AA64FPFR0_EL1)
    //                  || ImpDefBool("ID_AA64FPFR0_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64FPFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64FPFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64FPFR0_EL1;
}


/**
 * ID_AA64DFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64DFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,0));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,0));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64DFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64DFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64DFR0_EL1;
}


/**
 * ID_AA64DFR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64DFR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,1));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,1));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64DFR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64DFR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64DFR1_EL1;
}


/**
 * ID_AA64DFR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0101', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64DFR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,2));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,2));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_AA64DFR2_EL1)
    //                  || ImpDefBool("ID_AA64DFR2_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64DFR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64DFR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64DFR2_EL1;
}


/**
 * ID_AA64AFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0101', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64AFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,4));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,4));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64AFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64AFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64AFR0_EL1;
}


/**
 * ID_AA64AFR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64AFR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,5));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,5));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64AFR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64AFR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64AFR1_EL1;
}


/**
 * ID_AA64ISAR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64ISAR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,0));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,0));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64ISAR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64ISAR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64ISAR0_EL1;
}


/**
 * ID_AA64ISAR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64ISAR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,1));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,1));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64ISAR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64ISAR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64ISAR1_EL1;
}


/**
 * ID_AA64ISAR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0110', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64ISAR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,2));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,2));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_AA64ISAR2_EL1)
    //                  || ImpDefBool("ID_AA64ISAR2_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64ISAR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64ISAR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64ISAR2_EL1;
}


/**
 * ID_AA64ISAR3_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0110', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64ISAR3_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,3));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,3));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_AA64ISAR3_EL1)
    //                  || ImpDefBool("ID_AA64ISAR3_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64ISAR3_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64ISAR3_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64ISAR3_EL1;
}


/**
 * ID_AA64MMFR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64MMFR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,0));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,0));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64MMFR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64MMFR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64MMFR0_EL1;
}


/**
 * ID_AA64MMFR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64MMFR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,1));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,1));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64MMFR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64MMFR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64MMFR1_EL1;
}


/**
 * ID_AA64MMFR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0111', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64MMFR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,2));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,2));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_AA64MMFR2_EL1)
    //                  || ImpDefBool("ID_AA64MMFR2_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64MMFR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64MMFR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64MMFR2_EL1;
}


/**
 * ID_AA64MMFR3_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64MMFR3_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,3));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,3));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_AA64MMFR3_EL1)
    //                  || ImpDefBool("ID_AA64MMFR3_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64MMFR3_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64MMFR3_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64MMFR3_EL1;
}


/**
 * ID_AA64MMFR4_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0000', 'CRm': '0111', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ID_AA64MMFR4_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(18)/*TID3*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,4));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,4));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && (   IsFeatureImplemented(FEAT_FGT)
    //                  || !IsZero(AArch64.ID_AA64MMFR4_EL1)
    //                  || ImpDefBool("ID_AA64MMFR4_EL1 trapped by HCR_EL2.TID3"))
    //              && AArch64.HCR_EL2.TID3 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64MMFR4_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID3 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ID_AA64MMFR4_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ID_AA64MMFR4_EL1;
}


/**
 * SCTLR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x110, puDst);
        *puDst = pVCpu->cpum.GstCtx.Sctlr.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.SctlrEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Sctlr.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.SCTLR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x110>;
    //     else
    //         X<t,0x40> = SCTLR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SCTLR_EL2;
    //     else
    //         X<t,0x40> = SCTLR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLR_EL1;
}


/**
 * ACTLR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ACTLR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(21)/*TACR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x118, puDst);
        *puDst = pVCpu->cpum.GstCtx.Actlr.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Actlr.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TACR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EffectiveHCR_EL2_NVx() IN ('1x1')
    //              && (!ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") || EffectiveHCR_EL2_NVx() == '111'))
    //         X<t,0x40> = NVMem<0x118>;
    //     else
    //         X<t,0x40> = ACTLR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") && ELIsInHost(EL2))
    //         X<t,0x40> = ACTLR_EL2;
    //     else
    //         X<t,0x40> = ACTLR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ACTLR_EL1;
}


/**
 * CPACR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CPACR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(31)/*TCPAC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x100, puDst);
        *puDst = pVCpu->cpum.GstCtx.Cpacr.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.CptrEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Cpacr.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TCPAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.CPACR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x100>;
    //     else
    //         X<t,0x40> = CPACR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = CPTR_EL2;
    //     else
    //         X<t,0x40> = CPACR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CPACR_EL1;
}


/**
 * SCTLR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSctlr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x278, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3), "SCTLR2_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,3), "SCTLR2_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3), "SCTLR2_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SCTLR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.SCTLR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SCTLR2En == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x278>;
    //     else
    //         X<t,0x40> = SCTLR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = SCTLR2_EL2;
    //     else
    //         X<t,0x40> = SCTLR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLR2_EL1;
}


/**
 * RGSR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_RGSR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(56)/*ATA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,5), "RGSR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,5), "RGSR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.ATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = RGSR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = RGSR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = RGSR_EL1;
}


/**
 * GCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(56)/*ATA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,6), "GCR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,6), "GCR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.ATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = GCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = GCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GCR_EL1;
}


/**
 * ZCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ZCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSve)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 16) & UINT32_C(0x3)/*ZEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSve(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(8)/*TZ*/))
            return iemRaiseSystemAccessTrapSve(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 16) & UINT32_C(0x3)/*ZEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSve(pVCpu, 2);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1e0, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,0), "ZCR_EL1", puDst, uInstrEssence);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(8)/*TZ*/))
        return iemRaiseSystemAccessTrapSve(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 16) & UINT32_C(0x3)/*ZEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapSve(pVCpu, 2);
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,0), "ZCR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,0), "ZCR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SVE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.EZ == '0')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.ZEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 0x19)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.ZEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.EZ == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x19)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x1e0>;
    //     else
    //         X<t,0x40> = ZCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.EZ == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.ZEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.EZ == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x19)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = ZCR_EL2;
    //     else
    //         X<t,0x40> = ZCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.EZ == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x19)
    //     else
    //         X<t,0x40> = ZCR_EL1;
}


/**
 * TRFCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRFCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrf)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(19)/*TTRF*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x880, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,1), "TRFCR_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,1), "TRFCR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,1), "TRFCR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRF))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TTRF == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TTRF == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TTRF == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x880>;
    //     else
    //         X<t,0x40> = TRFCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TTRF == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TTRF == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = TRFCR_EL2;
    //     else
    //         X<t,0x40> = TRFCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TRFCR_EL1;
}


/**
 * TRCITECR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCITECR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fIte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x888, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,3), "TRCITECR_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,3), "TRCITECR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,3), "TRCITECR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ITE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnITE == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nTRCITECR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnITE == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x888>;
    //     else
    //         X<t,0x40> = TRCITECR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnITE == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnITE == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = TRCITECR_EL2;
    //     else
    //         X<t,0x40> = TRCITECR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TRCITECR_EL1;
}


/**
 * SMPRI_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SMPRI_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,4), "SMPRI_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,4), "SMPRI_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nSMPRI_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SMPRI_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SMPRI_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SMPRI_EL1;
}


/**
 * SMCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SMCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1f0, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,6), "SMCR_EL1", puDst, uInstrEssence);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,6), "SMCR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,6), "SMCR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 0x1d)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x1f0>;
    //     else
    //         X<t,0x40> = SMCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = SMCR_EL2;
    //     else
    //         X<t,0x40> = SMCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         X<t,0x40> = SMCR_EL1;
}


/**
 * SCTLRMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLRMASK_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x318, puDst);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,0),
                                     "SCTLRMASK_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,0),
                                     "SCTLRMASK_EL2",
                                     puDst,
                                     uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,0), "SCTLRMASK_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nSCTLRMASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x318>;
    //     else
    //         X<t,0x40> = SCTLRMASK_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = SCTLRMASK_EL2;
    //     else
    //         X<t,0x40> = SCTLRMASK_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLRMASK_EL1;
}


/**
 * ACTLRMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ACTLRMASK_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x340, puDst);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,1),
                                     "ACTLRMASK_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,1), "ACTLRMASK_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nACTLRMASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   EffectiveHCR_EL2_NVx() IN ('1x1')
    //              && (!ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") || EffectiveHCR_EL2_NVx() == '111'))
    //         X<t,0x40> = NVMem<0x340>;
    //     else
    //         X<t,0x40> = ACTLRMASK_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") && ELIsInHost(EL2))
    //         X<t,0x40> = ACTLRMASK_EL2;
    //     else
    //         X<t,0x40> = ACTLRMASK_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ACTLRMASK_EL1;
}


/**
 * CPACRMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CPACRMASK_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x320, puDst);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,2),
                                     "CPACRMASK_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,2), "CPTRMASK_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,2), "CPACRMASK_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nCPACRMASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x320>;
    //     else
    //         X<t,0x40> = CPACRMASK_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = CPTRMASK_EL2;
    //     else
    //         X<t,0x40> = CPACRMASK_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CPACRMASK_EL1;
}


/**
 * SCTLR2MASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR2MASK_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x328, puDst);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,3),
                                     "SCTLR2MASK_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,3),
                                     "SCTLR2MASK_EL2",
                                     puDst,
                                     uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,3), "SCTLR2MASK_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nSCTLR2MASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x328>;
    //     else
    //         X<t,0x40> = SCTLR2MASK_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = SCTLR2MASK_EL2;
    //     else
    //         X<t,0x40> = SCTLR2MASK_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLR2MASK_EL1;
}


/**
 * CPACRALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CPACRALIAS_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(31)/*TCPAC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x100, puDst);
        *puDst = pVCpu->cpum.GstCtx.Cpacr.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.CptrEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Cpacr.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TCPAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nCPACRALIAS_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x100>;
    //     else
    //         X<t,0x40> = CPACR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = CPTR_EL2;
    //     else
    //         X<t,0x40> = CPACR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CPACR_EL1;
}


/**
 * ACTLRALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ACTLRALIAS_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(21)/*TACR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x118, puDst);
        *puDst = pVCpu->cpum.GstCtx.Actlr.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Actlr.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TACR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nACTLRALIAS_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EffectiveHCR_EL2_NVx() IN ('1x1')
    //              && (!ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") || EffectiveHCR_EL2_NVx() == '111'))
    //         X<t,0x40> = NVMem<0x118>;
    //     else
    //         X<t,0x40> = ACTLR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") && ELIsInHost(EL2))
    //         X<t,0x40> = ACTLR_EL2;
    //     else
    //         X<t,0x40> = ACTLR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ACTLR_EL1;
}


/**
 * SCTLRALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLRALIAS_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x110, puDst);
        *puDst = pVCpu->cpum.GstCtx.Sctlr.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.SctlrEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Sctlr.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nSCTLRALIAS_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x110>;
    //     else
    //         X<t,0x40> = SCTLR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SCTLR_EL2;
    //     else
    //         X<t,0x40> = SCTLR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLR_EL1;
}


/**
 * SCTLR2ALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR2ALIAS_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSctlr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x278, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3), "SCTLR2_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,3), "SCTLR2_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3), "SCTLR2_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SCTLR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nSCTLRALIAS2_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SCTLR2En == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x278>;
    //     else
    //         X<t,0x40> = SCTLR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = SCTLR2_EL2;
    //     else
    //         X<t,0x40> = SCTLR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLR2_EL1;
}


/**
 * MAIR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MAIR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x140, puDst);
        *puDst = pVCpu->cpum.GstCtx.Mair.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.MairEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Mair.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.MAIR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x140>;
    //     else
    //         X<t,0x40> = MAIR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = MAIR_EL2;
    //     else
    //         X<t,0x40> = MAIR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MAIR_EL1;
}


/**
 * MAIR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MAIR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x280, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,1), "MAIR2_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,1,1), "MAIR2_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,1), "MAIR2_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nMAIR2_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x280>;
    //     else
    //         X<t,0x40> = MAIR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = MAIR2_EL2;
    //     else
    //         X<t,0x40> = MAIR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MAIR2_EL1;
}


/**
 * PIRE0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PIRE0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x290, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,2), "PIRE0_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,2), "PIRE0_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,2), "PIRE0_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nPIRE0_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x290>;
    //     else
    //         X<t,0x40> = PIRE0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = PIRE0_EL2;
    //     else
    //         X<t,0x40> = PIRE0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PIRE0_EL1;
}


/**
 * PIR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PIR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x2a0, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,3), "PIR_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,3), "PIR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,3), "PIR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nPIR_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x2a0>;
    //     else
    //         X<t,0x40> = PIR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = PIR_EL2;
    //     else
    //         X<t,0x40> = PIR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PIR_EL1;
}


/**
 * POR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_POR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Poe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x2a8, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,4), "POR_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,4), "POR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,4), "POR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nPOR_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x2a8>;
    //     else
    //         X<t,0x40> = POR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = POR_EL2;
    //     else
    //         X<t,0x40> = POR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = POR_EL1;
}


/**
 * S2POR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_S2POR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS2Poe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x2b8, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,5), "S2POR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,5), "S2POR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S2POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nS2POR_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x2b8>;
    //     else
    //         X<t,0x40> = S2POR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = S2POR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = S2POR_EL1;
}


/**
 * AMAIR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMAIR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x148, puDst);
        *puDst = pVCpu->cpum.GstCtx.Amair.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,0),
                                         "AMAIR_EL2",
                                         puDst,
                                         uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Amair.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.AMAIR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x148>;
    //     else
    //         X<t,0x40> = AMAIR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = AMAIR_EL2;
    //     else
    //         X<t,0x40> = AMAIR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMAIR_EL1;
}


/**
 * AMAIR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMAIR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x288, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,3,1), "AMAIR2_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,1), "AMAIR2_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,3,1), "AMAIR2_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nAMAIR2_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x288>;
    //     else
    //         X<t,0x40> = AMAIR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = AMAIR2_EL2;
    //     else
    //         X<t,0x40> = AMAIR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMAIR2_EL1;
}


/**
 * LORSA_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_LORSA_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fLor)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(35)/*TLOR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,0), "LORSA_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,0), "LORSA_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_LOR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TLOR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.LORSA_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = LORSA_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = LORSA_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = LORSA_EL1;
}


/**
 * LOREA_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_LOREA_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fLor)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(35)/*TLOR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,1), "LOREA_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,1), "LOREA_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_LOR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TLOR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.LOREA_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = LOREA_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = LOREA_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = LOREA_EL1;
}


/**
 * LORN_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_LORN_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fLor)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(35)/*TLOR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,2), "LORN_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,2), "LORN_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_LOR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TLOR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.LORN_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = LORN_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = LORN_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = LORN_EL1;
}


/**
 * LORC_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_LORC_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fLor)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(35)/*TLOR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,3), "LORC_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,3), "LORC_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_LOR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TLOR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.LORC_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = LORC_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = LORC_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = LORC_EL1;
}


/**
 * MPAMIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAMIDR_EL1.HAS_HCR == 1 && AArch64.MPAMHCR_EL2.TRAP_MPAMIDR_EL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.MPAMIDR_EL1.HAS_TIDR == 1 && AArch64.MPAM2_EL2.TIDR == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,4), "MPAMIDR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,4), "MPAMIDR_EL1", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && AArch64.MPAMHCR_EL2.TRAP_MPAMIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAMIDR_EL1.HAS_TIDR == '1' && AArch64.MPAM2_EL2.TIDR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = MPAMIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMIDR_EL1;
}


/**
 * MPAMBWIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0100', 'op2': '101'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMBWIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAMBW2_EL2.nTRAP_MPAMBWIDR_EL1 == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,5));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,5));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAMBW2_EL2.nTRAP_MPAMBWIDR_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = MPAMBWIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMBWIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMBWIDR_EL1;
}


/**
 * LORID_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_LORID_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fLor)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(35)/*TLOR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,7), "LORID_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,7), "LORID_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_LOR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TLOR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.LORID_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = LORID_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = LORID_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = LORID_EL1;
}


/**
 * MPAM1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAM1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAM2_EL2.TRAPMPAM1EL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x900, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,0), "MPAM1_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,0), "MPAM2_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,0), "MPAM1_EL1", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAM2_EL2.TRAPMPAM1EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x900>;
    //     else
    //         X<t,0x40> = MPAM1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = MPAM2_EL2;
    //     else
    //         X<t,0x40> = MPAM1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAM1_EL1;
}


/**
 * MPAM0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAM0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAM2_EL2.TRAPMPAM0EL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,1), "MPAM0_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,1), "MPAM0_EL1", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAM2_EL2.TRAPMPAM0EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = MPAM0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAM0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAM0_EL1;
}


/**
 * MPAMSM_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '011'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMSM_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || !pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAM2_EL2.EnMPAMSM == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,3), "MPAMSM_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,3), "MPAMSM_EL1", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && IsFeatureImplemented(FEAT_SME)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAM2_EL2.EnMPAMSM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = MPAMSM_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMSM_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMSM_EL1;
}


/**
 * MPAMBW1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '100'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMBW1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAMBW2_EL2.nTRAP_MPAMBW1_EL1 == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x908, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,4), "MPAMBW1_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,4), "MPAMBW2_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,4), "MPAMBW1_EL1", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAMBW2_EL2.nTRAP_MPAMBW1_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x908>;
    //     else
    //         X<t,0x40> = MPAMBW1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = MPAMBW2_EL2;
    //     else
    //         X<t,0x40> = MPAMBW1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMBW1_EL1;
}


/**
 * MPAMBW0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMBW0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAMBW2_EL2.nTRAP_MPAMBW0_EL1 == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,5), "MPAMBW0_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,5), "MPAMBW0_EL1", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAMBW2_EL2.nTRAP_MPAMBW0_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = MPAMBW0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMBW0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMBW0_EL1;
}


/**
 * MPAMBWSM_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '111'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMBWSM_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl || !pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAMBW2_EL2.nTRAP_MPAMBWSM_EL1 == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,7),
                                     "MPAMBWSM_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,7), "MPAMBWSM_EL1", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) && IsFeatureImplemented(FEAT_SME)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAMBW2_EL2.nTRAP_MPAMBWSM_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = MPAMBWSM_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMBWSM_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMBWSM_EL1;
}


/**
 * VBAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VBAR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x250, puDst);
        *puDst = pVCpu->cpum.GstCtx.VBar.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.VBarEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.VBar.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '011')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.VBAR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x250>;
    //     else
    //         X<t,0x40> = VBAR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = VBAR_EL2;
    //     else
    //         X<t,0x40> = VBAR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VBAR_EL1;
}


/**
 * RVBAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_RVBAR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1 && !pGstFeats->fEl2)
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,0,1), "RVBAR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsHighestEL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL1 && IsHighestEL(EL1))
    //     X<t,0x40> = RVBAR_EL1;
    // else
    //     Undefined()
}


/**
 * RMR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_RMR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1 && !pGstFeats->fEl2)
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,0,2), "RMR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsHighestEL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL1 && IsHighestEL(EL1))
    //     X<t,0x40> = RMR_EL1;
    // else
    //     Undefined()
}


/**
 * ISR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ISR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,1,0), "ISR_EL1", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,1,0), "ISR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGRTR_EL2.ISR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = ISR_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = ISR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ISR_EL1;
}


/**
 * DISR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DISR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !!(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(5)/*AMO*/))
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,1,1),
                                         "VDISR_EL2",
                                         puDst,
                                         uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,1,1), "DISR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,1,1), "DISR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && (   AArch64.HCR_EL2.AMO == '1'
    //             || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && AArch64.HCRX_EL2.TMEA == '1')))
    //         X<t,0x40> = VDISR_EL2;
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && AArch64.SCR_EL3.EnDSE == '1')
    //         X<t,0x40> = VDISR_EL3;
    //     else if (HaveEL(EL3) && !Halted() && AArch64.SCR_EL3.EA == '1')
    //         X<t,0x40> = Zeros(0x40);
    //     else
    //         X<t,0x40> = DISR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && AArch64.SCR_EL3.EnDSE == '1')
    //         X<t,0x40> = VDISR_EL3;
    //     else if (HaveEL(EL3) && !Halted() && AArch64.SCR_EL3.EA == '1')
    //         X<t,0x40> = Zeros(0x40);
    //     else
    //         X<t,0x40> = DISR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = DISR_EL1;
}


/**
 * ICC_RPR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1011', 'op2': '011'})
 * Transformation status: 5 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_RPR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TC == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            *puDst = ICV_RPR_EL1;
        else if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            *puDst = ICV_RPR_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,3),
                                         "ICC_RPR_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,3),
                                     "ICC_RPR_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         X<t,0x40> = ICV_RPR_EL1;
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         X<t,0x40> = ICV_RPR_EL1;
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_RPR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_RPR_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_RPR_EL1;
}


/**
 * ICC_IAR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '000'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_IAR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            *puDst = ICV_IAR1_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,0),
                                         "ICC_IAR1_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,0),
                                     "ICC_IAR1_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         X<t,0x40> = ICV_IAR1_EL1;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_IAR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_IAR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_IAR1_EL1;
}


/**
 * ICC_HPPIR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '010'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_HPPIR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            *puDst = ICV_HPPIR1_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,2),
                                         "ICC_HPPIR1_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,2),
                                     "ICC_HPPIR1_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         X<t,0x40> = ICV_HPPIR1_EL1;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_HPPIR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_HPPIR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_HPPIR1_EL1;
}


/**
 * ICC_BPR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '011'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_BPR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            *puDst = ICV_BPR1_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,3),
                                         "ICC_BPR1_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,3),
                                     "ICC_BPR1_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         X<t,0x40> = ICV_BPR1_EL1;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             X<t,0x40> = ICC_BPR1_EL1_S;
    //         else
    //             X<t,0x40> = ICC_BPR1_EL1_NS;
    //     else
    //         X<t,0x40> = ICC_BPR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             X<t,0x40> = ICC_BPR1_EL1_S;
    //         else
    //             X<t,0x40> = ICC_BPR1_EL1_NS;
    //     else
    //         X<t,0x40> = ICC_BPR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.SCR_EL3.NS == '0')
    //         X<t,0x40> = ICC_BPR1_EL1_S;
    //     else
    //         X<t,0x40> = ICC_BPR1_EL1_NS;
}


/**
 * ICC_CTLR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '100'})
 * Transformation status: 5 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_CTLR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TC == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            *puDst = ICV_CTLR_EL1;
        else if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            *puDst = ICV_CTLR_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,4),
                                         "ICC_CTLR_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,4),
                                     "ICC_CTLR_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         X<t,0x40> = ICV_CTLR_EL1;
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         X<t,0x40> = ICV_CTLR_EL1;
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             X<t,0x40> = ICC_CTLR_EL1_S;
    //         else
    //             X<t,0x40> = ICC_CTLR_EL1_NS;
    //     else
    //         X<t,0x40> = ICC_CTLR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             X<t,0x40> = ICC_CTLR_EL1_S;
    //         else
    //             X<t,0x40> = ICC_CTLR_EL1_NS;
    //     else
    //         X<t,0x40> = ICC_CTLR_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.SCR_EL3.NS == '0')
    //         X<t,0x40> = ICC_CTLR_EL1_S;
    //     else
    //         X<t,0x40> = ICC_CTLR_EL1_NS;
}


/**
 * ICC_SRE_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '101'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_SRE_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.ICC_SRE_EL2.Enable == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,5),
                                     "ICC_SRE_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,5), "ICC_SRE_EL1", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.ICC_SRE_EL3.Enable == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.ICC_SRE_EL2.Enable == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.ICC_SRE_EL3.Enable == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             X<t,0x40> = ICC_SRE_EL1_S;
    //         else
    //             X<t,0x40> = ICC_SRE_EL1_NS;
    //     else
    //         X<t,0x40> = ICC_SRE_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.ICC_SRE_EL3.Enable == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.ICC_SRE_EL3.Enable == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             X<t,0x40> = ICC_SRE_EL1_S;
    //         else
    //             X<t,0x40> = ICC_SRE_EL1_NS;
    //     else
    //         X<t,0x40> = ICC_SRE_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.NS == '0')
    //         X<t,0x40> = ICC_SRE_EL1_S;
    //     else
    //         X<t,0x40> = ICC_SRE_EL1_NS;
}


/**
 * ICC_IGRPEN0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '110'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_IGRPEN0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL0 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            *puDst = ICV_IGRPEN0_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,6),
                                         "ICC_IGRPEN0_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,6),
                                     "ICC_IGRPEN0_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ICC_IGRPENn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         X<t,0x40> = ICV_IGRPEN0_EL1;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_IGRPEN0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_IGRPEN0_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_IGRPEN0_EL1;
}


/**
 * ICC_IGRPEN1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '111'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_IGRPEN1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            *puDst = ICV_IGRPEN1_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,7),
                                         "ICC_IGRPEN1_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,7),
                                     "ICC_IGRPEN1_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ICC_IGRPENn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         X<t,0x40> = ICV_IGRPEN1_EL1;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             X<t,0x40> = ICC_IGRPEN1_EL1_S;
    //         else
    //             X<t,0x40> = ICC_IGRPEN1_EL1_NS;
    //     else
    //         X<t,0x40> = ICC_IGRPEN1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             X<t,0x40> = ICC_IGRPEN1_EL1_S;
    //         else
    //             X<t,0x40> = ICC_IGRPEN1_EL1_NS;
    //     else
    //         X<t,0x40> = ICC_IGRPEN1_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.SCR_EL3.NS == '0')
    //         X<t,0x40> = ICC_IGRPEN1_EL1_S;
    //     else
    //         X<t,0x40> = ICC_IGRPEN1_EL1_NS;
}


/**
 * ICC_IAR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1000', 'op2': '000'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_IAR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL0 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            *puDst = ICV_IAR0_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,0),
                                         "ICC_IAR0_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,0),
                                     "ICC_IAR0_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         X<t,0x40> = ICV_IAR0_EL1;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_IAR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_IAR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_IAR0_EL1;
}


/**
 * ICC_HPPIR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1000', 'op2': '010'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_HPPIR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL0 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            *puDst = ICV_HPPIR0_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,2),
                                         "ICC_HPPIR0_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,2),
                                     "ICC_HPPIR0_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         X<t,0x40> = ICV_HPPIR0_EL1;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_HPPIR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_HPPIR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_HPPIR0_EL1;
}


/**
 * ICC_BPR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1000', 'op2': '011'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_BPR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL0 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            *puDst = ICV_BPR0_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,3),
                                         "ICC_BPR0_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,3),
                                     "ICC_BPR0_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         X<t,0x40> = ICV_BPR0_EL1;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_BPR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_BPR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_BPR0_EL1;
}


/**
 * ICC_NMIAR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1001', 'op2': '101'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_NMIAR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3Nmi)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (!(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_64(61)/*NMI*/))
            return iemRaiseUndefined(pVCpu);
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            *puDst = ICV_NMIAR1_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,9,5),
                                         "ICC_NMIAR1_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (!(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_64(61)/*NMI*/))
            return iemRaiseUndefined(pVCpu);
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,9,5),
                                     "ICC_NMIAR1_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3_NMI))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (AArch64.SCTLR_EL1.NMI == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         X<t,0x40> = ICV_NMIAR1_EL1;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_NMIAR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (AArch64.SCTLR_EL2.NMI == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_NMIAR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCTLR_EL3.NMI == '0')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_NMIAR1_EL1;
}


/**
 * CONTEXTIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CONTEXTIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x108, puDst);
        *puDst = pVCpu->cpum.GstCtx.ContextIdr.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,1),
                                         "CONTEXTIDR_EL2",
                                         puDst,
                                         uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.ContextIdr.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.CONTEXTIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x108>;
    //     else
    //         X<t,0x40> = CONTEXTIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CONTEXTIDR_EL2;
    //     else
    //         X<t,0x40> = CONTEXTIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CONTEXTIDR_EL1;
}


/**
 * RCWSMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_RCWSMASK_EL1(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fThe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    *puDst = RCWSMASK_EL1<[0x3f:0]>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_THE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nRCWSMASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = RCWSMASK_EL1<[0x3f:0]>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = RCWSMASK_EL1<[0x3f:0]>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = RCWSMASK_EL1<[0x3f:0]>;
}


/**
 * TPIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TPIDR_EL1(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        *puDst = pVCpu->cpum.GstCtx.aTpIdr[1].u64;
    else
        *puDst = pVCpu->cpum.GstCtx.aTpIdr[1].u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGRTR_EL2.TPIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = TPIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = TPIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TPIDR_EL1;
}


/**
 * ACCDATA_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ACCDATA_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fLs64Accdata)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,5), "ACCDATA_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,5), "ACCDATA_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_LS64_ACCDATA))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ADEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nACCDATA_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ADEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ACCDATA_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ADEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ADEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ACCDATA_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ACCDATA_EL1;
}


/**
 * RCWMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 6 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_RCWMASK_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fThe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = RCWMASK_EL1<[0x3f:0]>;
    }
    else
        *puDst = RCWMASK_EL1<[0x3f:0]>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_THE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nRCWMASK_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = RCWMASK_EL1<[0x3f:0]>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = RCWMASK_EL1<[0x3f:0]>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = RCWMASK_EL1<[0x3f:0]>;
}


/**
 * SCXTNUM_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCXTNUM_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fCvs2_2 && !pGstFeats->fCsv21p2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(53)/*EnSCXT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x188, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,7), "SCXTNUM_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,7), "SCXTNUM_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,7), "SCXTNUM_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_CSV2_2) || IsFeatureImplemented(FEAT_CSV2_1p2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() == '011')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.EnSCXT == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.SCXTNUM_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x188>;
    //     else
    //         X<t,0x40> = SCXTNUM_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = SCXTNUM_EL2;
    //     else
    //         X<t,0x40> = SCXTNUM_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCXTNUM_EL1;
}


/**
 * CNTKCTL_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1110', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 2 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTKCTL_EL1(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        *puDst = pVCpu->cpum.GstCtx.CntKCtl.u64;
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = CNTHCTL_EL2_VHE(CNTHCTL_EL2);
        else
            *puDst = pVCpu->cpum.GstCtx.CntKCtl.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = CNTKCTL_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CNTHCTL_EL2_VHE(CNTHCTL_EL2);
    //     else
    //         X<t,0x40> = CNTKCTL_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTKCTL_EL1;
}


/**
 * TTBR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TTBR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x200, puDst);
        *puDst = pVCpu->cpum.GstCtx.Ttbr0.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.Ttbr0El2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Ttbr0.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.TTBR0_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x200>;
    //     else
    //         X<t,0x40> = TTBR0_EL1<[0x3f:0]>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TTBR0_EL2<[0x3f:0]>;
    //     else
    //         X<t,0x40> = TTBR0_EL1<[0x3f:0]>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TTBR0_EL1<[0x3f:0]>;
}


/**
 * TTBR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TTBR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x210, puDst);
        *puDst = pVCpu->cpum.GstCtx.Ttbr1.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.Ttbr1El2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Ttbr1.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.TTBR1_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x210>;
    //     else
    //         X<t,0x40> = TTBR1_EL1<[0x3f:0]>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TTBR1_EL2<[0x3f:0]>;
    //     else
    //         X<t,0x40> = TTBR1_EL1<[0x3f:0]>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TTBR1_EL1<[0x3f:0]>;
}


/**
 * TCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x120, puDst);
        *puDst = pVCpu->cpum.GstCtx.Tcr.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.TcrEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Tcr.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.TCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x120>;
    //     else
    //         X<t,0x40> = TCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TCR_EL2;
    //     else
    //         X<t,0x40> = TCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TCR_EL1;
}


/**
 * TCR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTcr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x270, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3), "TCR2_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,3), "TCR2_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3), "TCR2_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TCR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.TCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.TCR2En == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x270>;
    //     else
    //         X<t,0x40> = TCR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = TCR2_EL2;
    //     else
    //         X<t,0x40> = TCR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TCR2_EL1;
}


/**
 * APIAKeyLo_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_APIAKeyLo_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Apia.Low.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Apia.Low.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.APIAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APIAKeyLo_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APIAKeyLo_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = APIAKeyLo_EL1;
}


/**
 * APIAKeyHi_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_APIAKeyHi_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Apia.High.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Apia.High.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.APIAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APIAKeyHi_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APIAKeyHi_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = APIAKeyHi_EL1;
}


/**
 * APIBKeyLo_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_APIBKeyLo_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Apib.Low.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Apib.Low.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.APIBKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APIBKeyLo_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APIBKeyLo_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = APIBKeyLo_EL1;
}


/**
 * APIBKeyHi_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_APIBKeyHi_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Apib.High.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Apib.High.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.APIBKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APIBKeyHi_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APIBKeyHi_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = APIBKeyHi_EL1;
}


/**
 * APDAKeyLo_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_APDAKeyLo_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Apda.Low.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Apda.Low.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.APDAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APDAKeyLo_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APDAKeyLo_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = APDAKeyLo_EL1;
}


/**
 * APDAKeyHi_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_APDAKeyHi_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Apda.High.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Apda.High.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.APDAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APDAKeyHi_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APDAKeyHi_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = APDAKeyHi_EL1;
}


/**
 * APDBKeyLo_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_APDBKeyLo_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Apdb.Low.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Apdb.Low.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.APDBKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APDBKeyLo_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APDBKeyLo_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = APDBKeyLo_EL1;
}


/**
 * APDBKeyHi_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_APDBKeyHi_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Apdb.High.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Apdb.High.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.APDBKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APDBKeyHi_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APDBKeyHi_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = APDBKeyHi_EL1;
}


/**
 * APGAKeyLo_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_APGAKeyLo_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Apga.Low.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Apga.Low.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.APGAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APGAKeyLo_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APGAKeyLo_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = APGAKeyLo_EL1;
}


/**
 * APGAKeyHi_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_APGAKeyHi_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Apga.High.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Apga.High.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.APGAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APGAKeyHi_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = APGAKeyHi_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = APGAKeyHi_EL1;
}


/**
 * GCSCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GCSCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x8d0, puDst);
        *puDst = 0;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = 0;
        else
            *puDst = 0;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nGCS_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x8d0>;
    //     else
    //         X<t,0x40> = GCSCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = GCSCR_EL2;
    //     else
    //         X<t,0x40> = GCSCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GCSCR_EL1;
}


/**
 * GCSPR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GCSPR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x8c0, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,1), "GCSPR_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,5,1), "GCSPR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,1), "GCSPR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nGCS_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x8c0>;
    //     else
    //         X<t,0x40> = GCSPR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = GCSPR_EL2;
    //     else
    //         X<t,0x40> = GCSPR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GCSPR_EL1;
}


/**
 * GCSCRE0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0101', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GCSCRE0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = 0;
    }
    else
        *puDst = 0;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nGCS_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = GCSCRE0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = GCSCRE0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GCSCRE0_EL1;
}


/**
 * TCRMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0111', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCRMASK_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x330, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,2), "TCRMASK_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,2), "TCRMASK_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,2), "TCRMASK_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nTCRMASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x330>;
    //     else
    //         X<t,0x40> = TCRMASK_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = TCRMASK_EL2;
    //     else
    //         X<t,0x40> = TCRMASK_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TCRMASK_EL1;
}


/**
 * TCR2MASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCR2MASK_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x338, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,3), "TCR2MASK_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,3), "TCR2MASK_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,3), "TCR2MASK_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nTCR2MASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x338>;
    //     else
    //         X<t,0x40> = TCR2MASK_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = TCR2MASK_EL2;
    //     else
    //         X<t,0x40> = TCR2MASK_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TCR2MASK_EL1;
}


/**
 * TCRALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0111', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCRALIAS_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x120, puDst);
        *puDst = pVCpu->cpum.GstCtx.Tcr.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.TcrEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Tcr.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nTCRALIAS_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x120>;
    //     else
    //         X<t,0x40> = TCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TCR_EL2;
    //     else
    //         X<t,0x40> = TCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TCR_EL1;
}


/**
 * TCR2ALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0111', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCR2ALIAS_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTcr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x270, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3), "TCR2_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,3), "TCR2_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3), "TCR2_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TCR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nTCR2ALIAS_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.TCR2En == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x270>;
    //     else
    //         X<t,0x40> = TCR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = TCR2_EL2;
    //     else
    //         X<t,0x40> = TCR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TCR2_EL1;
}


/**
 * SPSR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPSR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x160, puDst);
        *puDst = pVCpu->cpum.GstCtx.Spsr.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.SpsrEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Spsr.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '011')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x160>;
    //     else
    //         X<t,0x40> = SPSR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SPSR_EL2;
    //     else
    //         X<t,0x40> = SPSR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPSR_EL1;
}


/**
 * ELR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ELR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x230, puDst);
        *puDst = pVCpu->cpum.GstCtx.Elr.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.ElrEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Elr.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '011')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x230>;
    //     else
    //         X<t,0x40> = ELR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = ELR_EL2;
    //     else
    //         X<t,0x40> = ELR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ELR_EL1;
}


/**
 * SP_EL0 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SP_EL0(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (!(pVCpu->cpum.GstCtx.fPState & UINT64_C(0x1)/*SP*/))
        return iemRaiseUndefined(pVCpu);
    *puDst = pVCpu->cpum.GstCtx.aSpReg[0].u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (PSTATE.SP == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = SP_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (PSTATE.SP == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = SP_EL0;
    // else if (PSTATE.EL == EL3)
    //     if (PSTATE.SP == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = SP_EL0;
}


/**
 * SPSel - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPSel(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x1)/*SP*/);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = (Zeros(0x3f)):(PSTATE.SP);
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = (Zeros(0x3f)):(PSTATE.SP);
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = (Zeros(0x3f)):(PSTATE.SP);
}


/**
 * CurrentEL - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CurrentEL(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            *puDst = 8;
        else
            *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xc)/*EL*/);
    }
    else
        *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xc)/*EL*/);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         X<t,0x40> = (Zeros(0x3c)):('10'):(Zeros(2));
    //     else
    //         X<t,0x40> = (Zeros(0x3c)):(PSTATE.EL):(Zeros(2));
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = (Zeros(0x3c)):(PSTATE.EL):(Zeros(2));
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = (Zeros(0x3c)):(PSTATE.EL):(Zeros(2));
}


/**
 * PAN - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PAN(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPan)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000)/*PAN*/);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAN))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = (Zeros(0x29)):(PSTATE.PAN):(Zeros(0x16));
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = (Zeros(0x29)):(PSTATE.PAN):(Zeros(0x16));
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = (Zeros(0x29)):(PSTATE.PAN):(Zeros(0x16));
}


/**
 * UAO - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_UAO(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fUao)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x800000)/*UAO*/);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_UAO))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = (Zeros(0x28)):(PSTATE.UAO):(Zeros(0x17));
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = (Zeros(0x28)):(PSTATE.UAO):(Zeros(0x17));
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = (Zeros(0x28)):(PSTATE.UAO):(Zeros(0x17));
}


/**
 * ALLINT - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ALLINT(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fNmi)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x2000)/*ALLINT*/);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_NMI))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = (Zeros(0x32)):(PSTATE.ALLINT):(Zeros(0xd));
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = (Zeros(0x32)):(PSTATE.ALLINT):(Zeros(0xd));
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = (Zeros(0x32)):(PSTATE.ALLINT):(Zeros(0xd));
}


/**
 * PM - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PM(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEbep)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x100000000)/*PM*/);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_EBEP))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = (Zeros(0x1f)):(PSTATE.PM):(Zeros(0x20));
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = (Zeros(0x1f)):(PSTATE.PM):(Zeros(0x20));
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = (Zeros(0x1f)):(PSTATE.PM):(Zeros(0x20));
}


/**
 * ICC_PMR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 5 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_PMR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TC == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            *puDst = ICV_PMR_EL1;
        else if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            *puDst = ICV_PMR_EL1;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,6,0),
                                         "ICC_PMR_EL1",
                                         puDst,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,6,0), "ICC_PMR_EL1", puDst, uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         X<t,0x40> = ICV_PMR_EL1;
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         X<t,0x40> = ICV_PMR_EL1;
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_PMR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_PMR_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_PMR_EL1;
}


/**
 * AFSR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AFSR0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x128, puDst);
        *puDst = pVCpu->cpum.GstCtx.Afsr0.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,0),
                                         "AFSR0_EL2",
                                         puDst,
                                         uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Afsr0.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.AFSR0_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x128>;
    //     else
    //         X<t,0x40> = AFSR0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = AFSR0_EL2;
    //     else
    //         X<t,0x40> = AFSR0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AFSR0_EL1;
}


/**
 * AFSR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AFSR1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x130, puDst);
        *puDst = pVCpu->cpum.GstCtx.Afsr1.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,1),
                                         "AFSR1_EL2",
                                         puDst,
                                         uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Afsr1.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.AFSR1_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x130>;
    //     else
    //         X<t,0x40> = AFSR1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = AFSR1_EL2;
    //     else
    //         X<t,0x40> = AFSR1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AFSR1_EL1;
}


/**
 * ESR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ESR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x138, puDst);
        *puDst = pVCpu->cpum.GstCtx.Esr.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.EsrEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Esr.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ESR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x138>;
    //     else
    //         X<t,0x40> = ESR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = ESR_EL2;
    //     else
    //         X<t,0x40> = ESR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ESR_EL1;
}


/**
 * ERRIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERRIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,0));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,0));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERRIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERRIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERRIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERRIDR_EL1;
}


/**
 * ERRSELR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERRSELR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,1), "ERRSELR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,1), "ERRSELR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERRSELR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERRSELR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERRSELR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERRSELR_EL1;
}


/**
 * ERXGSR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXGSR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRasV2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,2), "ERXGSR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,2), "ERXGSR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RASv2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nERXGSR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXGSR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXGSR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXGSR_EL1;
}


/**
 * ERXFR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXFR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,0), "ERXFR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,0), "ERXFR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERXFR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXFR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXFR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXFR_EL1;
}


/**
 * ERXCTLR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXCTLR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,1), "ERXCTLR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,1), "ERXCTLR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERXCTLR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXCTLR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXCTLR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXCTLR_EL1;
}


/**
 * ERXSTATUS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXSTATUS_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,2),
                                     "ERXSTATUS_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,2), "ERXSTATUS_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERXSTATUS_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXSTATUS_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXSTATUS_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXSTATUS_EL1;
}


/**
 * ERXADDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXADDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,3), "ERXADDR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,3), "ERXADDR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERXADDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXADDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXADDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXADDR_EL1;
}


/**
 * ERXPFGF_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXPFGF_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRasV1p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(47)/*FIEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,4), "ERXPFGF_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,4), "ERXPFGF_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RASv1p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIEN == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FIEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERXPFGF_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIEN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXPFGF_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIEN == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIEN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXPFGF_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXPFGF_EL1;
}


/**
 * ERXPFGCTL_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXPFGCTL_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRasV1p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(47)/*FIEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,5),
                                     "ERXPFGCTL_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,5), "ERXPFGCTL_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RASv1p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIEN == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FIEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERXPFGCTL_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIEN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXPFGCTL_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIEN == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIEN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXPFGCTL_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXPFGCTL_EL1;
}


/**
 * ERXPFGCDN_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXPFGCDN_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRasV1p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(47)/*FIEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,6),
                                     "ERXPFGCDN_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,6), "ERXPFGCDN_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RASv1p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIEN == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FIEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERXPFGCDN_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIEN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXPFGCDN_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIEN == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIEN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXPFGCDN_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXPFGCDN_EL1;
}


/**
 * ERXMISC0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXMISC0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,0), "ERXMISC0_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,0), "ERXMISC0_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERXMISCn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXMISC0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXMISC0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXMISC0_EL1;
}


/**
 * ERXMISC1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXMISC1_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,1), "ERXMISC1_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,1), "ERXMISC1_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERXMISCn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXMISC1_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXMISC1_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXMISC1_EL1;
}


/**
 * ERXMISC2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0101', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXMISC2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRasV1p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,2), "ERXMISC2_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,2), "ERXMISC2_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RASv1p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERXMISCn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXMISC2_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXMISC2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXMISC2_EL1;
}


/**
 * ERXMISC3_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ERXMISC3_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRasV1p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,3), "ERXMISC3_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,3), "ERXMISC3_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RASv1p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.ERXMISCn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXMISC3_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ERXMISC3_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ERXMISC3_EL1;
}


/**
 * TFSR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TFSR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(56)/*ATA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x190, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,0), "TFSR_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,6,0), "TFSR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,0), "TFSR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() == '011')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.ATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x190>;
    //     else
    //         X<t,0x40> = TFSR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = TFSR_EL2;
    //     else
    //         X<t,0x40> = TFSR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TFSR_EL1;
}


/**
 * TFSRE0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TFSRE0_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(56)/*ATA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,1), "TFSRE0_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,1), "TFSRE0_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.ATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TFSRE0_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TFSRE0_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TFSRE0_EL1;
}


/**
 * FAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0110', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_FAR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x220, puDst);
        *puDst = pVCpu->cpum.GstCtx.Far.u64;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.FarEl2.u64;
        else
            *puDst = pVCpu->cpum.GstCtx.Far.u64;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.FAR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x220>;
    //     else
    //         X<t,0x40> = FAR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = FAR_EL2;
    //     else
    //         X<t,0x40> = FAR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = FAR_EL1;
}


/**
 * PFAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0110', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PFAR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPfar)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x2d0, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,6,0,5), "PFAR_EL1", puDst, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,6,0,5), "PFAR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,6,0,5), "PFAR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PFAR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PFAREn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nPFAR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PFAREn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x2d0>;
    //     else
    //         X<t,0x40> = PFAR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PFAREn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PFAREn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = PFAR_EL2;
    //     else
    //         X<t,0x40> = PFAR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PFAR_EL1;
}


/**
 * PAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0111', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PAR_EL1(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        *puDst = pVCpu->cpum.GstCtx.Par.u64;
    else
        *puDst = pVCpu->cpum.GstCtx.Par.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGRTR_EL2.PAR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = PAR_EL1<[0x3f:0]>;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = PAR_EL1<[0x3f:0]>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PAR_EL1<[0x3f:0]>;
}


/**
 * PMBLIMITR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMBLIMITR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 12) & UINT32_C(0x3)/*E2PB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x800, puDst);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,0),
                                     "PMBLIMITR_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,0), "PMBLIMITR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMBLIMITR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2PB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x800>;
    //     else
    //         X<t,0x40> = PMBLIMITR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMBLIMITR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMBLIMITR_EL1;
}


/**
 * PMBPTR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMBPTR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 12) & UINT32_C(0x3)/*E2PB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x810, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,1), "PMBPTR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,1), "PMBPTR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMBPTR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2PB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x810>;
    //     else
    //         X<t,0x40> = PMBPTR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMBPTR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMBPTR_EL1;
}


/**
 * PMBSR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1010', 'op2': '011'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMBSR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 12) & UINT32_C(0x3)/*E2PB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x820, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,3), "PMBSR_EL1", puDst, uInstrEssence);
    }
    if (   EffectivePMSCR_EL2_EE() != 0
        && pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,10,3), "PMBSR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,3), "PMBSR_EL1", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMBSR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2PB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   EffectiveHCR_EL2_NVx() IN ('1x1')
    //              && (EffectivePMSCR_EL2_EE() == '00' || AArch64.PMSCR_EL1.EE == '00' || EffectiveHCR_EL2_NVx() == '111'))
    //         X<t,0x40> = NVMem<0x820>;
    //     else
    //         X<t,0x40> = PMBSR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectivePMSCR_EL2_EE() != '00' && ELIsInHost(EL2))
    //         X<t,0x40> = PMBSR_EL2;
    //     else
    //         X<t,0x40> = PMBSR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMBSR_EL1;
}


/**
 * PMSDSFR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSDSFR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpeFds)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x858, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,4), "PMSDSFR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,4), "PMSDSFR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE_FDS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMS3 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMSDSFR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMS3 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x858>;
    //     else
    //         X<t,0x40> = PMSDSFR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMS3 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMS3 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSDSFR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSDSFR_EL1;
}


/**
 * PMBMAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMBMAR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpeNvm)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 12) & UINT32_C(0x3)/*E2PB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,5), "PMBMAR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,5), "PMBMAR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE_nVM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMS4 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMBMAR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2PB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMS4 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMBMAR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMS4 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMS4 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMBMAR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMBMAR_EL1;
}


/**
 * PMBIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1010', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMBIDR_EL1(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,7));
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,7));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HDFGRTR_EL2.PMBIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = PMBIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = PMBIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMBIDR_EL1;
}


/**
 * TRBLIMITR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRBLIMITR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,0),
                                     "TRBLIMITR_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,0), "TRBLIMITR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRBLIMITR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBLIMITR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBLIMITR_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBLIMITR_EL1;
}


/**
 * TRBPTR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRBPTR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,1), "TRBPTR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,1), "TRBPTR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRBPTR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBPTR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBPTR_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBPTR_EL1;
}


/**
 * TRBBASER_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRBBASER_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,2),
                                     "TRBBASER_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,2), "TRBBASER_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRBBASER_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBBASER_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBBASER_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBBASER_EL1;
}


/**
 * TRBSR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '011'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRBSR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7 && EffectiveTRFCR_EL2_EE() != 0 && AArch64.TRFCR_EL1.EE != 0)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x860, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,3), "TRBSR_EL1", puDst, uInstrEssence);
    }
    if (   EffectiveTRFCR_EL2_EE() != 0
        && pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,11,3), "TRBSR_EL2", puDst, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,3), "TRBSR_EL1", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRBSR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111') && EffectiveTRFCR_EL2_EE() != '00' && AArch64.TRFCR_EL1.EE != '00')
    //         X<t,0x40> = NVMem<0x860>;
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBSR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else if (EffectiveTRFCR_EL2_EE() != '00' && ELIsInHost(EL2))
    //         X<t,0x40> = TRBSR_EL2;
    //     else
    //         X<t,0x40> = TRBSR_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBSR_EL1;
}


/**
 * TRBMAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRBMAR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,4), "TRBMAR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,4), "TRBMAR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRBMAR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBMAR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBMAR_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBMAR_EL1;
}


/**
 * TRBMPAM_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRBMPAM_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbeMpam)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,5), "TRBMPAM_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,5), "TRBMPAM_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnTB2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nTRBMPAM_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnTB2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBMPAM_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnTB2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnTB2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBMPAM_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBMPAM_EL1;
}


/**
 * TRBTRG_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRBTRG_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,6), "TRBTRG_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,6), "TRBTRG_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.TRBTRG_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBTRG_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBTRG_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBTRG_EL1;
}


/**
 * TRBIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRBIDR_EL1(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,7));
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,7));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HDFGRTR_EL2.TRBIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         X<t,0x40> = TRBIDR_EL1;
}


/**
 * PMSSCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSSCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3Ss)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,13,3), "PMSSCR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3_SS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSS == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMSSCR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSSCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSSCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSSCR_EL1;
}


/**
 * PMINTENSET_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMINTENSET_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,1),
                                     "PMINTENSET_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,1), "PMINTENSET_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMINTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMINTENSET_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMINTENSET_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMINTENSET_EL1;
}


/**
 * PMINTENCLR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMINTENCLR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,2),
                                     "PMINTENCLR_EL1",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,2), "PMINTENCLR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMINTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMINTENCLR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMINTENCLR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMINTENCLR_EL1;
}


/**
 * PMUACR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMUACR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3p9)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,4), "PMUACR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,4), "PMUACR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3p9))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMUACR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMUACR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMUACR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMUACR_EL1;
}


/**
 * PMECR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMECR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEbep && !pGstFeats->fPmuV3Ss)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,5), "PMECR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,5), "PMECR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_EBEP) || IsFeatureImplemented(FEAT_PMUv3_SS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMECR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMECR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMECR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMECR_EL1;
}


/**
 * PMMIR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMMIR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3p4)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,6));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,6));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3p4))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMMIR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMMIR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMMIR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMMIR_EL1;
}


/**
 * PMIAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMIAR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSebep)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,7), "PMIAR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,7), "PMIAR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SEBEP))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMIAR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMIAR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMIAR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMIAR_EL1;
}


/**
 * PMSCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x828, puDst);
        *puDst = 0;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,9,0),
                                         "PMSCR_EL2",
                                         puDst,
                                         uInstrEssence);
        *puDst = 0;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMSCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x828>;
    //     else
    //         X<t,0x40> = PMSCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         X<t,0x40> = PMSCR_EL2;
    //     else
    //         X<t,0x40> = PMSCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSCR_EL1;
}


/**
 * PMSNEVFR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSNEVFR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpeFnE)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x850, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,1), "PMSNEVFR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,1), "PMSNEVFR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE_FnE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSN == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.nPMSNEVFR_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x850>;
    //     else
    //         X<t,0x40> = PMSNEVFR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSN == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSNEVFR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSNEVFR_EL1;
}


/**
 * PMSICR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSICR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x838, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,2), "PMSICR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,2), "PMSICR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMSICR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x838>;
    //     else
    //         X<t,0x40> = PMSICR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSICR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSICR_EL1;
}


/**
 * PMSIRR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSIRR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x840, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,3), "PMSIRR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,3), "PMSIRR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMSIRR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x840>;
    //     else
    //         X<t,0x40> = PMSIRR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSIRR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSIRR_EL1;
}


/**
 * PMSFCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSFCR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,4), "PMSFCR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,4), "PMSFCR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMSFCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSFCR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSFCR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSFCR_EL1;
}


/**
 * PMSEVFR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSEVFR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x830, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,5), "PMSEVFR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,5), "PMSEVFR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMSEVFR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x830>;
    //     else
    //         X<t,0x40> = PMSEVFR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSEVFR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSEVFR_EL1;
}


/**
 * PMSLATFR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSLATFR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x848, puDst);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,6), "PMSLATFR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,6), "PMSLATFR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMSLATFR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x848>;
    //     else
    //         X<t,0x40> = PMSLATFR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSLATFR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSLATFR_EL1;
}


/**
 * PMSIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,7));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,7));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMSIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSIDR_EL1;
}


/**
 * CCSIDR_EL1 - OrderedDict({'op0': '11', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CCSIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(17)/*TID2*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fEvt && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(49)/*TID4*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,0), "CCSIDR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,0), "CCSIDR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TID2 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_EVT) && AArch64.HCR_EL2.TID4 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.CCSIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = CCSIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CCSIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CCSIDR_EL1;
}


/**
 * CLIDR_EL1 - OrderedDict({'op0': '11', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CLIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(17)/*TID2*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fEvt && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(49)/*TID4*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,1), "CLIDR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,1), "CLIDR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TID2 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_EVT) && AArch64.HCR_EL2.TID4 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.CLIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = CLIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CLIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CLIDR_EL1;
}


/**
 * CCSIDR2_EL1 - OrderedDict({'op0': '11', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CCSIDR2_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fCcidx)
        UnimplementedIDRegister()
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(17)/*TID2*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fEvt && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(49)/*TID4*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,2), "CCSIDR2_EL1", puDst, uInstrEssence);
    }
    else
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,2), "CCSIDR2_EL1", puDst, uInstrEssence);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_CCIDX))
    //     UnimplementedIDRegister()
    // else if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TID2 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_EVT) && AArch64.HCR_EL2.TID4 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = CCSIDR2_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CCSIDR2_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CCSIDR2_EL1;
}


/**
 * GMID_EL1 - OrderedDict({'op0': '11', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '100'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GMID_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        UnimplementedIDRegister()
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(58)/*TID5*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,4));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,4));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     UnimplementedIDRegister()
    // else if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID5 == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TID5 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID5 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = GMID_EL1;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID5 == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && AArch64.SCR_EL3.TID5 == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = GMID_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GMID_EL1;
}


/**
 * SMIDR_EL1 - OrderedDict({'op0': '11', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SMIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        UnimplementedIDRegister()
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(16)/*TID1*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,6));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,6));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     UnimplementedIDRegister()
    // else if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TID1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = SMIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = SMIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SMIDR_EL1;
}


/**
 * AIDR_EL1 - OrderedDict({'op0': '11', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AIDR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fIdst)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        return iemRaiseUndefined(pVCpu);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(16)/*TID1*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,7), "AIDR_EL1", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,7), "AIDR_EL1", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_IDST))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TID1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.AIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = AIDR_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = AIDR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AIDR_EL1;
}


/**
 * CSSELR_EL1 - OrderedDict({'op0': '11', 'op1': '010', 'CRn': '0000', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CSSELR_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(17)/*TID2*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fEvt && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(49)/*TID4*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.Csselr.u64;
    }
    else
        *puDst = pVCpu->cpum.GstCtx.Csselr.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TID2 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_EVT) && AArch64.HCR_EL2.TID4 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.CSSELR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = CSSELR_EL1;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CSSELR_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CSSELR_EL1;
}


/**
 * CTR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0000', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CTR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(15)/*UCT*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(17)/*TID2*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(15)/*UCT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,0,0,1));
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(17)/*TID2*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,0,0,1));
    }
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,0,0,1));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCT == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TID2 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.CTR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCT == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = CTR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TID2 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.CTR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = CTR_EL0;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CTR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CTR_EL0;
}


/**
 * DCZID_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0000', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DCZID_EL0(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,0,0,7));
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,0,0,7));
    else
        *puDst = iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,0,0,7));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (   EL2Enabled()
    //         && !ELIsInHost(EL0)
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGRTR_EL2.DCZID_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = DCZID_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGRTR_EL2.DCZID_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = DCZID_EL0;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = DCZID_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = DCZID_EL0;
}


/**
 * POR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1010', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_POR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Poe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(29)/*E0POE*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(29)/*E0POE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,10,2,4), "POR_EL0", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(30)/*TRVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,10,2,4), "POR_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,10,2,4), "POR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.CPACR_EL1.E0POE == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nPOR_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CPTR_EL2.E0POE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = POR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nPOR_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = POR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = POR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = POR_EL0;
}


/**
 * TPIDR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TPIDR_EL0(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        *puDst = pVCpu->cpum.GstCtx.aTpIdr[0].u64;
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        *puDst = pVCpu->cpum.GstCtx.aTpIdr[0].u64;
    else
        *puDst = pVCpu->cpum.GstCtx.aTpIdr[0].u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (   EL2Enabled()
    //         && !ELIsInHost(EL0)
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGRTR_EL2.TPIDR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = TPIDR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGRTR_EL2.TPIDR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = TPIDR_EL0;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = TPIDR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TPIDR_EL0;
}


/**
 * TPIDRRO_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TPIDRRO_EL0(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        *puDst = pVCpu->cpum.GstCtx.TpIdrRoEl0.u64;
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        *puDst = pVCpu->cpum.GstCtx.TpIdrRoEl0.u64;
    else
        *puDst = pVCpu->cpum.GstCtx.TpIdrRoEl0.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (   EL2Enabled()
    //         && !ELIsInHost(EL0)
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGRTR_EL2.TPIDRRO_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = TPIDRRO_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGRTR_EL2.TPIDRRO_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = TPIDRRO_EL0;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = TPIDRRO_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TPIDRRO_EL0;
}


/**
 * TPIDR2_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TPIDR2_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_64(60)/*EnTP2*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_64(60)/*EnTP2*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,5), "TPIDR2_EL0", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,5), "TPIDR2_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,5), "TPIDR2_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnTP2 == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.EnTP2 == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.EnTP2 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nTPIDR2_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnTP2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TPIDR2_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnTP2 == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nTPIDR2_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnTP2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TPIDR2_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnTP2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnTP2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TPIDR2_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TPIDR2_EL0;
}


/**
 * SCXTNUM_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCXTNUM_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fCvs2_2 && !pGstFeats->fCsv21p2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(20)/*TSCXT*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(53)/*EnSCXT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && (pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(20)/*TSCXT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,7), "SCXTNUM_EL0", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(53)/*EnSCXT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,7), "SCXTNUM_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,7), "SCXTNUM_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_CSV2_2) || IsFeatureImplemented(FEAT_CSV2_1p2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.TSCXT == '1')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.EnSCXT == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.SCXTNUM_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.TSCXT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SCXTNUM_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.EnSCXT == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.SCXTNUM_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SCXTNUM_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SCXTNUM_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCXTNUM_EL0;
}


/**
 * AMCR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMCR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(30)/*TAM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,0), "AMCR_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,0), "AMCR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (AArch64.AMUSERENR_EL0.EN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMCR_EL0;
}


/**
 * AMCFGR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMCFGR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(30)/*TAM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,1), "AMCFGR_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,1), "AMCFGR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (AArch64.AMUSERENR_EL0.EN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCFGR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCFGR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCFGR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMCFGR_EL0;
}


/**
 * AMCGCR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMCGCR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(30)/*TAM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,2), "AMCGCR_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,2), "AMCGCR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (AArch64.AMUSERENR_EL0.EN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCGCR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCGCR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCGCR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMCGCR_EL0;
}


/**
 * AMUSERENR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMUSERENR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(30)/*TAM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = 0;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(30)/*TAM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = 0;
    }
    else
        *puDst = 0;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMUSERENR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMUSERENR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMUSERENR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMUSERENR_EL0;
}


/**
 * AMCNTENCLR0_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMCNTENCLR0_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(30)/*TAM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt && AArch64.HAFGRTR_EL2.AMCNTEN0 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,4),
                                     "AMCNTENCLR0_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,4), "AMCNTENCLR0_EL0", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (AArch64.AMUSERENR_EL0.EN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HAFGRTR_EL2.AMCNTEN0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENCLR0_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HAFGRTR_EL2.AMCNTEN0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENCLR0_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENCLR0_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMCNTENCLR0_EL0;
}


/**
 * AMCNTENSET0_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMCNTENSET0_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(30)/*TAM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt && AArch64.HAFGRTR_EL2.AMCNTEN0 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,5),
                                     "AMCNTENSET0_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,5), "AMCNTENSET0_EL0", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (AArch64.AMUSERENR_EL0.EN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HAFGRTR_EL2.AMCNTEN0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENSET0_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HAFGRTR_EL2.AMCNTEN0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENSET0_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENSET0_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMCNTENSET0_EL0;
}


/**
 * AMCG1IDR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMCG1IDR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(30)/*TAM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,6),
                                     "AMCG1IDR_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,6), "AMCG1IDR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (AArch64.AMUSERENR_EL0.EN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCG1IDR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCG1IDR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCG1IDR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMCG1IDR_EL0;
}


/**
 * AMCNTENCLR1_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMCNTENCLR1_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(30)/*TAM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt && AArch64.HAFGRTR_EL2.AMCNTEN1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,3,0),
                                     "AMCNTENCLR1_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,3,0), "AMCNTENCLR1_EL0", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (AArch64.AMUSERENR_EL0.EN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HAFGRTR_EL2.AMCNTEN1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENCLR1_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HAFGRTR_EL2.AMCNTEN1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENCLR1_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENCLR1_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMCNTENCLR1_EL0;
}


/**
 * AMCNTENSET1_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMCNTENSET1_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(30)/*TAM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt && AArch64.HAFGRTR_EL2.AMCNTEN1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,3,1),
                                     "AMCNTENSET1_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,3,1), "AMCNTENSET1_EL0", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (AArch64.AMUSERENR_EL0.EN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HAFGRTR_EL2.AMCNTEN1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENSET1_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HAFGRTR_EL2.AMCNTEN1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENSET1_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMCNTENSET1_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMCNTENSET1_EL0;
}


/**
 * CNTFRQ_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTFRQ_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & UINT64_C(0x3) /*EL0PCTEN,EL0VCTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & UINT64_C(0x3) /*EL0PCTEN,EL0VCTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,0,0), "CNTFRQ_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,0,0), "CNTFRQ_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && (AArch64.CNTKCTL_EL1.EL0PCTEN):(AArch64.CNTKCTL_EL1.EL0VCTEN) == '00')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && (AArch64.CNTHCTL_EL2.EL0PCTEN):(AArch64.CNTHCTL_EL2.EL0VCTEN) == '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = CNTFRQ_EL0;
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = CNTFRQ_EL0;
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CNTFRQ_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTFRQ_EL0;
}


/**
 * CNTPCT_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTPCT_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & UINT32_C(1)/*EL0PCTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & UINT32_C(1)/*EL1PCTEN_AT_00*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(10)/*EL1PCTEN_AT_10*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & UINT32_C(1)/*EL0PCTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & UINT32_C(1)/*EL1PCTEN_AT_00*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    else
        *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0PCTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.HCR_EL2.TGE == '0' && AArch64.CNTHCTL_EL2.EL1PCTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0PCTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_ECV_POFF)
    //              && EL2Enabled()
    //              && SCR_EL3.ECVEn == '1'
    //              && CNTHCTL_EL2.ECV == '1'
    //              && !ELIsInHost(EL0))
    //         X<t,0x40> = PhysicalCountInt() - CNTPOFF_EL2;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.CNTHCTL_EL2.EL1PCTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1')
    //         X<t,0x40> = PhysicalCountInt() - CNTPOFF_EL2;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PhysicalCountInt();
}


/**
 * CNTVCT_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTVCT_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(1)/*EL0VCTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL0VCTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(14)/*EL1TVCT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)))
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu) - pVCpu->cpum.GstCtx.CntVOffEl2.u64;
        else
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(14)/*EL1TVCT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu) - pVCpu->cpum.GstCtx.CntVOffEl2.u64;
        else
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    else
    {
        if (   !pGstFeats->fVhe
            || !pGstFeats->fEl2
            || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu) - pVCpu->cpum.GstCtx.CntVOffEl2.u64;
        else
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0VCTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0VCTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL1TVCT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL2) && (!EL2Enabled() || !ELIsInHost(EL0)))
    //         X<t,0x40> = PhysicalCountInt() - CNTVOFF_EL2;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.CNTHCTL_EL2.EL1TVCT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL2))
    //         X<t,0x40> = PhysicalCountInt() - CNTVOFF_EL2;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL2)
    //     if (!ELIsInHost(EL2))
    //         X<t,0x40> = PhysicalCountInt() - CNTVOFF_EL2;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL3)
    //     if (HaveEL(EL2) && !ELUsingAArch32(EL2))
    //         X<t,0x40> = PhysicalCountInt() - CNTVOFF_EL2;
    //     else if (HaveEL(EL2) && ELUsingAArch32(EL2))
    //         X<t,0x40> = PhysicalCountInt() - CNTVOFF;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
}


/**
 * CNTPCTSS_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTPCTSS_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEcv)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & UINT32_C(1)/*EL0PCTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & UINT32_C(1)/*EL1PCTEN_AT_00*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(10)/*EL1PCTEN_AT_10*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & UINT32_C(1)/*EL0PCTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & UINT32_C(1)/*EL1PCTEN_AT_00*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    else
        *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_ECV))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0PCTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.HCR_EL2.TGE == '0' && AArch64.CNTHCTL_EL2.EL1PCTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0PCTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_ECV_POFF)
    //              && EL2Enabled()
    //              && SCR_EL3.ECVEn == '1'
    //              && CNTHCTL_EL2.ECV == '1'
    //              && !ELIsInHost(EL0))
    //         X<t,0x40> = PhysicalCountInt() - CNTPOFF_EL2;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.CNTHCTL_EL2.EL1PCTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (IsFeatureImplemented(FEAT_ECV_POFF) && EL2Enabled() && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1')
    //         X<t,0x40> = PhysicalCountInt() - CNTPOFF_EL2;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PhysicalCountInt();
}


/**
 * CNTVCTSS_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTVCTSS_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEcv)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(1)/*EL0VCTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL0VCTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(14)/*EL1TVCT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)))
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu) - pVCpu->cpum.GstCtx.CntVOffEl2.u64;
        else
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(14)/*EL1TVCT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu) - pVCpu->cpum.GstCtx.CntVOffEl2.u64;
        else
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    else
    {
        if (   !pGstFeats->fVhe
            || !pGstFeats->fEl2
            || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu) - pVCpu->cpum.GstCtx.CntVOffEl2.u64;
        else
            *puDst = iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_ECV))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0VCTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0VCTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL1TVCT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL2) && (!EL2Enabled() || !ELIsInHost(EL0)))
    //         X<t,0x40> = PhysicalCountInt() - CNTVOFF_EL2;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.CNTHCTL_EL2.EL1TVCT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL2))
    //         X<t,0x40> = PhysicalCountInt() - CNTVOFF_EL2;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL2)
    //     if (!ELIsInHost(EL2))
    //         X<t,0x40> = PhysicalCountInt() - CNTVOFF_EL2;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
    // else if (PSTATE.EL == EL3)
    //     if (HaveEL(EL2) && !ELUsingAArch32(EL2))
    //         X<t,0x40> = PhysicalCountInt() - CNTVOFF_EL2;
    //     else if (HaveEL(EL2) && ELUsingAArch32(EL2))
    //         X<t,0x40> = PhysicalCountInt() - CNTVOFF;
    //     else
    //         X<t,0x40> = PhysicalCountInt();
}


/**
 * PMCCFILTR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '1111', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMCCFILTR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fPmuV3p9
            && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)
            && !(iemCImplHlpGetPmUacrEl1(pVCpu) & RT_BIT_32(31)/*C*/))
            *puDst = 0;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7),
                                         "PMCCFILTR_EL0",
                                         puDst,
                                         uInstrEssence);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7),
                                     "PMCCFILTR_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    else
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7),
                                     "PMCCFILTR_EL0",
                                     puDst,
                                     uInstrEssence);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCCFILTR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1' && PMUACR_EL1.C == '0')
    //         X<t,0x40> = Zeros(0x40);
    //     else
    //         X<t,0x40> = PMCCFILTR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCCFILTR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCCFILTR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCCFILTR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMCCFILTR_EL0;
}


/**
 * CNTP_TVAL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTP_TVAL_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(9)/*EL0PTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(9)/*EL0PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        {
            if (!(pVCpu->cpum.GstCtx.CntHpCtlEl2.u64 & UINT32_C(1)/*ENABLE*/))
                *puDst = 0;
            else
                *puDst = (uint64_t)(uint32_t)(pVCpu->cpum.GstCtx.CntHpCValEl2.u64 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu));
        }
        else
            *puDst = 0;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        *puDst = 0;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        {
            if (!(pVCpu->cpum.GstCtx.CntHpCtlEl2.u64 & UINT32_C(1)/*ENABLE*/))
                *puDst = 0;
            else
                *puDst = (uint64_t)(uint32_t)(pVCpu->cpum.GstCtx.CntHpCValEl2.u64 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu));
        }
        else
            *puDst = 0;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0PTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.HCR_EL2.TGE == '0' && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         if (CNTHPS_CTL_EL2.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTHPS_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         if (CNTHP_CTL_EL2.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTHP_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    //     else if (   IsFeatureImplemented(FEAT_ECV_POFF)
    //              && EL2Enabled()
    //              && SCR_EL3.ECVEn == '1'
    //              && CNTHCTL_EL2.ECV == '1'
    //              && !ELIsInHost(EL0))
    //         if (AArch64.CNTP_CTL_EL0.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTP_CVAL_EL0 - PhysicalCountInt() - CNTPOFF_EL2)<[0x1f:0]>, 0x40);
    //     else if (CNTP_CTL_EL0.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTP_CVAL_EL0 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_ECV_POFF)
    //              && EL2Enabled()
    //              && AArch64.SCR_EL3.ECVEn == '1'
    //              && AArch64.CNTHCTL_EL2.ECV == '1')
    //         if (AArch64.CNTP_CTL_EL0.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTP_CVAL_EL0 - PhysicalCountInt() - CNTPOFF_EL2)<[0x1f:0]>, 0x40);
    //     else if (CNTP_CTL_EL0.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTP_CVAL_EL0 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         if (CNTHPS_CTL_EL2.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTHPS_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         if (CNTHP_CTL_EL2.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTHP_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    //     else if (CNTP_CTL_EL0.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTP_CVAL_EL0 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    // else if (PSTATE.EL == EL3)
    //     if (CNTP_CTL_EL0.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTP_CVAL_EL0 - PhysicalCountInt())<[0x1f:0]>, 0x40);
}


/**
 * CNTP_CTL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTP_CTL_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(9)/*EL0PTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(9)/*EL0PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            *puDst = pVCpu->cpum.GstCtx.CntHpCtlEl2.u64;
        else
            *puDst = 0;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x180, puDst);
        *puDst = 0;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.CntHpCtlEl2.u64;
        else
            *puDst = 0;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0PTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.HCR_EL2.TGE == '0' && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         X<t,0x40> = CNTHPS_CTL_EL2;
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         X<t,0x40> = CNTHP_CTL_EL2;
    //     else
    //         X<t,0x40> = CNTP_CTL_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x180>;
    //     else
    //         X<t,0x40> = CNTP_CTL_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         X<t,0x40> = CNTHPS_CTL_EL2;
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         X<t,0x40> = CNTHP_CTL_EL2;
    //     else
    //         X<t,0x40> = CNTP_CTL_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTP_CTL_EL0;
}


/**
 * CNTP_CVAL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTP_CVAL_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(9)/*EL0PTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(9)/*EL0PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            *puDst = pVCpu->cpum.GstCtx.CntHpCValEl2.u64;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                         "CNTP_CVAL_EL0",
                                         puDst,
                                         uInstrEssence);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x178, puDst);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                     "CNTP_CVAL_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            *puDst = pVCpu->cpum.GstCtx.CntHpCValEl2.u64;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                         "CNTP_CVAL_EL0",
                                         puDst,
                                         uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0PTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.HCR_EL2.TGE == '0' && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         X<t,0x40> = CNTHPS_CVAL_EL2;
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         X<t,0x40> = CNTHP_CVAL_EL2;
    //     else
    //         X<t,0x40> = CNTP_CVAL_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x178>;
    //     else
    //         X<t,0x40> = CNTP_CVAL_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         X<t,0x40> = CNTHPS_CVAL_EL2;
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         X<t,0x40> = CNTHP_CVAL_EL2;
    //     else
    //         X<t,0x40> = CNTP_CVAL_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTP_CVAL_EL0;
}


/**
 * CNTV_TVAL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 10 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTV_TVAL_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(8)/*EL0VTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(8)/*EL0VTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && pGstFeats->fEcv
            && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        {
            if (AArch64.CNTHV_CTL_EL2.ENABLE == 0)
                *puDst = 0;
            else
                *puDst = ZeroExtend((CNTHV_CVAL_EL2 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu))<[0x1f:0]>, 0x40);
        }
        else if (   pGstFeats->fEl2
                 && (   !pGstFeats->fVhe
                     || !pGstFeats->fEl2
                     || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                     || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)))
        {
            if (!(pVCpu->cpum.GstCtx.CntvCtlEl0 & UINT32_C(1)/*ENABLE*/))
                *puDst = 0;
            else
                *puDst = (uint64_t)(uint32_t)(pVCpu->cpum.GstCtx.CntvCValEl0 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu) - pVCpu->cpum.GstCtx.CntVOffEl2.u64);
        }
        else if (!(pVCpu->cpum.GstCtx.CntvCtlEl0 & UINT32_C(1)/*ENABLE*/))
            *puDst = 0;
        else
            *puDst = (uint64_t)(uint32_t)(pVCpu->cpum.GstCtx.CntvCValEl0 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu));
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fEcv && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
        {
            if (!(pVCpu->cpum.GstCtx.CntvCtlEl0 & UINT32_C(1)/*ENABLE*/))
                *puDst = 0;
            else
                *puDst = (uint64_t)(uint32_t)(pVCpu->cpum.GstCtx.CntvCValEl0 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu) - pVCpu->cpum.GstCtx.CntVOffEl2.u64);
        }
        else if (!(pVCpu->cpum.GstCtx.CntvCtlEl0 & UINT32_C(1)/*ENABLE*/))
            *puDst = 0;
        else
            *puDst = (uint64_t)(uint32_t)(pVCpu->cpum.GstCtx.CntvCValEl0 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu));
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        {
            if (AArch64.CNTHV_CTL_EL2.ENABLE == 0)
                *puDst = 0;
            else
                *puDst = ZeroExtend((CNTHV_CVAL_EL2 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu))<[0x1f:0]>, 0x40);
        }
        else if (   !pGstFeats->fVhe
                 || !pGstFeats->fEl2
                 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        {
            if (!(pVCpu->cpum.GstCtx.CntvCtlEl0 & UINT32_C(1)/*ENABLE*/))
                *puDst = 0;
            else
                *puDst = (uint64_t)(uint32_t)(pVCpu->cpum.GstCtx.CntvCValEl0 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu) - pVCpu->cpum.GstCtx.CntVOffEl2.u64);
        }
        else if (!(pVCpu->cpum.GstCtx.CntvCtlEl0 & UINT32_C(1)/*ENABLE*/))
            *puDst = 0;
        else
            *puDst = (uint64_t)(uint32_t)(pVCpu->cpum.GstCtx.CntvCValEl0 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu));
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0VTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0VTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         if (CNTHVS_CTL_EL2.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTHVS_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         if (CNTHV_CTL_EL2.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTHV_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    //     else if (HaveEL(EL2) && !ELIsInHost(EL0))
    //         if (CNTV_CTL_EL0.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTV_CVAL_EL0 - PhysicalCountInt() - CNTVOFF_EL2)<[0x1f:0]>, 0x40);
    //     else if (CNTV_CTL_EL0.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTV_CVAL_EL0 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL2))
    //         if (CNTV_CTL_EL0.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTV_CVAL_EL0 - PhysicalCountInt() - CNTVOFF_EL2)<[0x1f:0]>, 0x40);
    //     else if (CNTV_CTL_EL0.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTV_CVAL_EL0 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         if (CNTHVS_CTL_EL2.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTHVS_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         if (CNTHV_CTL_EL2.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTHV_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    //     else if (!ELIsInHost(EL2))
    //         if (CNTV_CTL_EL0.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTV_CVAL_EL0 - PhysicalCountInt() - CNTVOFF_EL2)<[0x1f:0]>, 0x40);
    //     else if (CNTV_CTL_EL0.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTV_CVAL_EL0 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    // else if (PSTATE.EL == EL3)
    //     if (CNTV_CTL_EL0.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else if (HaveEL(EL2) && !ELUsingAArch32(EL2))
    //         X<t,0x40> = ZeroExtend((CNTV_CVAL_EL0 - PhysicalCountInt() - CNTVOFF_EL2)<[0x1f:0]>, 0x40);
    //     else if (HaveEL(EL2) && ELUsingAArch32(EL2))
    //         X<t,0x40> = ZeroExtend((CNTV_CVAL_EL0 - PhysicalCountInt() - CNTVOFF)<[0x1f:0]>, 0x40);
    //     else
    //         X<t,0x40> = ZeroExtend((CNTV_CVAL_EL0 - PhysicalCountInt())<[0x1f:0]>, 0x40);
}


/**
 * CNTV_CTL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTV_CTL_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(8)/*EL0VTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(8)/*EL0VTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && pGstFeats->fEcv
            && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,1),
                                         "CNTHV_CTL_EL2",
                                         puDst,
                                         uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.CntvCtlEl0;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fEcv && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x170, puDst);
        *puDst = pVCpu->cpum.GstCtx.CntvCtlEl0;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,1),
                                         "CNTHV_CTL_EL2",
                                         puDst,
                                         uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.CntvCtlEl0;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0VTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0VTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         X<t,0x40> = CNTHVS_CTL_EL2;
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         X<t,0x40> = CNTHV_CTL_EL2;
    //     else
    //         X<t,0x40> = CNTV_CTL_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x170>;
    //     else
    //         X<t,0x40> = CNTV_CTL_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         X<t,0x40> = CNTHVS_CTL_EL2;
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         X<t,0x40> = CNTHV_CTL_EL2;
    //     else
    //         X<t,0x40> = CNTV_CTL_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTV_CTL_EL0;
}


/**
 * CNTV_CVAL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTV_CVAL_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(8)/*EL0VTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(8)/*EL0VTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && pGstFeats->fEcv
            && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,2),
                                         "CNTHV_CVAL_EL2",
                                         puDst,
                                         uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.CntvCValEl0;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fEcv && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x168, puDst);
        *puDst = pVCpu->cpum.GstCtx.CntvCValEl0;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,2),
                                         "CNTHV_CVAL_EL2",
                                         puDst,
                                         uInstrEssence);
        *puDst = pVCpu->cpum.GstCtx.CntvCValEl0;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0VTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0VTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         X<t,0x40> = CNTHVS_CVAL_EL2;
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         X<t,0x40> = CNTHV_CVAL_EL2;
    //     else
    //         X<t,0x40> = CNTV_CVAL_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         X<t,0x40> = NVMem<0x168>;
    //     else
    //         X<t,0x40> = CNTV_CVAL_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         X<t,0x40> = CNTHVS_CVAL_EL2;
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         X<t,0x40> = CNTHV_CVAL_EL2;
    //     else
    //         X<t,0x40> = CNTV_CVAL_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTV_CVAL_EL0;
}


/**
 * RNDR - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0010', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_RNDR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRng && !pGstFeats->fRngTrap)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fRng)
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,2,4,0), "RNDR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_RNG) || IsFeatureImplemented(FEAT_RNG_TRAP)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_RNG_TRAP) && AArch64.SCR_EL3.TRNDR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsFeatureImplemented(FEAT_RNG))
    //         Undefined()
    //     else
    //         X<t,0x40> = RNDR;
    // else if (PSTATE.EL == EL1)
    //     if (IsFeatureImplemented(FEAT_RNG_TRAP) && AArch64.SCR_EL3.TRNDR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsFeatureImplemented(FEAT_RNG))
    //         Undefined()
    //     else
    //         X<t,0x40> = RNDR;
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_RNG_TRAP) && AArch64.SCR_EL3.TRNDR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsFeatureImplemented(FEAT_RNG))
    //         Undefined()
    //     else
    //         X<t,0x40> = RNDR;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RNG_TRAP) && AArch64.SCR_EL3.TRNDR == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsFeatureImplemented(FEAT_RNG))
    //         Undefined()
    //     else
    //         X<t,0x40> = RNDR;
}


/**
 * RNDRRS - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0010', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_RNDRRS(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRng && !pGstFeats->fRngTrap)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fRng)
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,2,4,1), "RNDRRS", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_RNG) || IsFeatureImplemented(FEAT_RNG_TRAP)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (IsFeatureImplemented(FEAT_RNG_TRAP) && AArch64.SCR_EL3.TRNDR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsFeatureImplemented(FEAT_RNG))
    //         Undefined()
    //     else
    //         X<t,0x40> = RNDRRS;
    // else if (PSTATE.EL == EL1)
    //     if (IsFeatureImplemented(FEAT_RNG_TRAP) && AArch64.SCR_EL3.TRNDR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsFeatureImplemented(FEAT_RNG))
    //         Undefined()
    //     else
    //         X<t,0x40> = RNDRRS;
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_RNG_TRAP) && AArch64.SCR_EL3.TRNDR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsFeatureImplemented(FEAT_RNG))
    //         Undefined()
    //     else
    //         X<t,0x40> = RNDRRS;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RNG_TRAP) && AArch64.SCR_EL3.TRNDR == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsFeatureImplemented(FEAT_RNG))
    //         Undefined()
    //     else
    //         X<t,0x40> = RNDRRS;
}


/**
 * GCSPR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GCSPR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!pGstFeats->fEl2 || ((pVCpu->cpum.GstCtx.HcrEl2.u64 >> 27) & UINT32_C(1)/*TGE*/) != 1)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,2,5,1), "GCSPR_EL0", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,2,5,1), "GCSPR_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,2,5,1), "GCSPR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if ((!EL2Enabled() || AArch64.HCR_EL2.TGE != '1') && AArch64.GCSCRE0_EL1.nTR == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1' && AArch64.GCSCRE0_EL1.nTR == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nGCS_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = GCSPR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGRTR_EL2.nGCS_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = GCSPR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = GCSPR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GCSPR_EL0;
}


/**
 * NZCV - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_NZCV(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xf0000000)/*N,Z,C,V*/);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     X<t,0x40> = (Zeros(0x20)):((PSTATE.N):(PSTATE.Z):(PSTATE.C):(PSTATE.V)):(Zeros(0x1c));
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = (Zeros(0x20)):((PSTATE.N):(PSTATE.Z):(PSTATE.C):(PSTATE.V)):(Zeros(0x1c));
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = (Zeros(0x20)):((PSTATE.N):(PSTATE.Z):(PSTATE.C):(PSTATE.V)):(Zeros(0x1c));
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = (Zeros(0x20)):((PSTATE.N):(PSTATE.Z):(PSTATE.C):(PSTATE.V)):(Zeros(0x1c));
}


/**
 * DAIF - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DAIF(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   pGstFeats->fVhe
                && pGstFeats->fEl2
                && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            || !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(9)/*UMA*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x3c0)/*D,A,I,F*/);
    }
    else
        *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x3c0)/*D,A,I,F*/);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (ELIsInHost(EL0) || AArch64.SCTLR_EL1.UMA == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         X<t,0x40> = (Zeros(0x36)):((PSTATE.D):(PSTATE.A):(PSTATE.I):(PSTATE.F)):(Zeros(6));
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = (Zeros(0x36)):((PSTATE.D):(PSTATE.A):(PSTATE.I):(PSTATE.F)):(Zeros(6));
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = (Zeros(0x36)):((PSTATE.D):(PSTATE.A):(PSTATE.I):(PSTATE.F)):(Zeros(6));
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = (Zeros(0x36)):((PSTATE.D):(PSTATE.A):(PSTATE.I):(PSTATE.F)):(Zeros(6));
}


/**
 * SVCR - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SVCR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && ((pVCpu->cpum.GstCtx.Cpacr.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrapSme(pVCpu, 2);
            return iemRaiseSystemAccessTrapSme(pVCpu, 1);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && ((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) != 3)
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,2), "SVCR", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,2), "SVCR", puDst, uInstrEssence);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,2), "SVCR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.CPACR_EL1.SMEN != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x1d)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x1d)
    //     else if (ELIsInHost(EL0) && AArch64.CPTR_EL2.SMEN != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         X<t,0x40> = SVCR;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 0x1d)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         X<t,0x40> = SVCR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         X<t,0x40> = SVCR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         X<t,0x40> = SVCR;
}


/**
 * DIT - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DIT(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fDit)
        return iemRaiseUndefined(pVCpu);
    *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x1000000)/*DIT*/);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_DIT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     X<t,0x40> = (Zeros(0x27)):(PSTATE.DIT):(Zeros(0x18));
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = (Zeros(0x27)):(PSTATE.DIT):(Zeros(0x18));
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = (Zeros(0x27)):(PSTATE.DIT):(Zeros(0x18));
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = (Zeros(0x27)):(PSTATE.DIT):(Zeros(0x18));
}


/**
 * SSBS - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SSBS(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSsbs2)
        return iemRaiseUndefined(pVCpu);
    *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x1000)/*SSBS*/);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SSBS2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     X<t,0x40> = (Zeros(0x33)):(PSTATE.SSBS):(Zeros(0xc));
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = (Zeros(0x33)):(PSTATE.SSBS):(Zeros(0xc));
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = (Zeros(0x33)):(PSTATE.SSBS):(Zeros(0xc));
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = (Zeros(0x33)):(PSTATE.SSBS):(Zeros(0xc));
}


/**
 * TCO - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCO(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    *puDst = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x2000000)/*TCO*/);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     X<t,0x40> = (Zeros(0x26)):(PSTATE.TCO):(Zeros(0x19));
    // else if (PSTATE.EL == EL1)
    //     X<t,0x40> = (Zeros(0x26)):(PSTATE.TCO):(Zeros(0x19));
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = (Zeros(0x26)):(PSTATE.TCO):(Zeros(0x19));
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = (Zeros(0x26)):(PSTATE.TCO):(Zeros(0x19));
}


/**
 * FPCR - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_FPCR(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && ((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrapUnknown(pVCpu, 2);
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && ((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        *puDst = pVCpu->cpum.GstCtx.fpcr;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        *puDst = pVCpu->cpum.GstCtx.fpcr;
    }
    else
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        *puDst = pVCpu->cpum.GstCtx.fpcr;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.CPACR_EL1.FPEN != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 7)
    //     else if (ELIsInHost(EL0) && AArch64.CPTR_EL2.FPEN != '11')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPCR;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPCR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPCR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TFP == '1')
    //         AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPCR;
}


/**
 * FPSR - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_FPSR(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && ((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrapUnknown(pVCpu, 2);
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && ((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        *puDst = pVCpu->cpum.GstCtx.fpsr;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        *puDst = pVCpu->cpum.GstCtx.fpsr;
    }
    else
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        *puDst = pVCpu->cpum.GstCtx.fpsr;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.CPACR_EL1.FPEN != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 7)
    //     else if (ELIsInHost(EL0) && AArch64.CPTR_EL2.FPEN != '11')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPSR;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPSR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPSR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TFP == '1')
    //         AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPSR;
}


/**
 * FPMR - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_FPMR(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFpmr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_64(34)/*EnFPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_64(34)/*EnFPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && ((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrapUnknown(pVCpu, 2);
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && ((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,2), "FPMR", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,2), "FPMR", puDst, uInstrEssence);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
        return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,2), "FPMR", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FPMR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnFPM == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.EnFPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.EnFPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && AArch64.SCR_EL3.HXEn == '0') || AArch64.HCRX_EL2.EnFPM == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnFPM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!ELIsInHost(EL0) && AArch64.CPACR_EL1.FPEN != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 7)
    //     else if (ELIsInHost(EL0) && AArch64.CPTR_EL2.FPEN != '11')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPMR;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnFPM == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && AArch64.SCR_EL3.HXEn == '0') || AArch64.HCRX_EL2.EnFPM == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnFPM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.CPACR_EL1.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPMR;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnFPM == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnFPM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPMR;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TFP == '1')
    //         AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPMR;
}


/**
 * DSPSR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DSPSR_EL0(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!Halted())
    //     Undefined()
    // else
    //     X<t,0x40> = DSPSR_EL0;
}


/**
 * DLR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DLR_EL0(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!Halted())
    //     Undefined()
    // else
    //     X<t,0x40> = DLR_EL0;
}


/**
 * PMCR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMCR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            || (pGstFeats->fPmuV3p9 && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(5)/*TPMCR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,0), "PMCR_EL0", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(5)/*TPMCR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,0), "PMCR_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,0), "PMCR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' || (IsFeatureImplemented(FEAT_PMUv3p9) && AArch64.PMUSERENR_EL0.UEN == '1'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMCR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMCR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMCR_EL0;
}


/**
 * PMCNTENSET_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMCNTENSET_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,1),
                                     "PMCNTENSET_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,1),
                                     "PMCNTENSET_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,1), "PMCNTENSET_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCNTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCNTENSET_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCNTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCNTENSET_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCNTENSET_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMCNTENSET_EL0;
}


/**
 * PMCNTENCLR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMCNTENCLR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,2),
                                     "PMCNTENCLR_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,2),
                                     "PMCNTENCLR_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,2), "PMCNTENCLR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCNTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCNTENCLR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCNTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCNTENCLR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCNTENCLR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMCNTENCLR_EL0;
}


/**
 * PMOVSCLR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMOVSCLR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,3),
                                     "PMOVSCLR_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,3),
                                     "PMOVSCLR_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,3), "PMOVSCLR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMOVS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMOVSCLR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMOVS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMOVSCLR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMOVSCLR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMOVSCLR_EL0;
}


/**
 * PMSELR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSELR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (pGstFeats->fPmuV3p9 && !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT64_C(0x19) /*UEN,ER,EN*/))
            || (!pGstFeats->fPmuV3p9 && !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT64_C(0x9) /*ER,EN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,5), "PMSELR_EL0", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,5), "PMSELR_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,5), "PMSELR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   (   IsFeatureImplemented(FEAT_PMUv3p9)
    //                  && (AArch64.PMUSERENR_EL0.UEN):(AArch64.PMUSERENR_EL0.ER):(AArch64.PMUSERENR_EL0.EN) == '000')
    //              || (!IsFeatureImplemented(FEAT_PMUv3p9) && (AArch64.PMUSERENR_EL0.ER):(AArch64.PMUSERENR_EL0.EN) == '00'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMSELR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSELR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMSELR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSELR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSELR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSELR_EL0;
}


/**
 * PMCEID0_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMCEID0_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fPmuV3p9 && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(6)/*TID*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,6), "PMCEID0_EL0", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,6), "PMCEID0_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,6), "PMCEID0_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (IsFeatureImplemented(FEAT_PMUv3p9) && AArch64.PMUSERENR_EL0.TID == '1')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCEIDn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCEID0_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCEIDn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCEID0_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCEID0_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMCEID0_EL0;
}


/**
 * PMCEID1_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMCEID1_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fPmuV3p9 && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(6)/*TID*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,7), "PMCEID1_EL0", puDst, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,7), "PMCEID1_EL0", puDst, uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,7), "PMCEID1_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (IsFeatureImplemented(FEAT_PMUv3p9) && AArch64.PMUSERENR_EL0.TID == '1')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCEIDn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCEID1_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCEIDn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCEID1_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCEID1_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMCEID1_EL0;
}


/**
 * PMCCNTR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMCCNTR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (pGstFeats->fPmuV3p9 && !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT64_C(0x15) /*UEN,CR,EN*/))
            || (!pGstFeats->fPmuV3p9 && !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT64_C(0x5) /*CR,EN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fPmuV3p9
            && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)
            && !(iemCImplHlpGetPmUacrEl1(pVCpu) & RT_BIT_32(31)/*C*/))
            *puDst = 0;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,0),
                                         "PMCCNTR_EL0",
                                         puDst,
                                         uInstrEssence);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,0), "PMCCNTR_EL0", puDst, uInstrEssence);
    }
    else
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,0), "PMCCNTR_EL0", puDst, uInstrEssence);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   (   IsFeatureImplemented(FEAT_PMUv3p9)
    //                  && (AArch64.PMUSERENR_EL0.UEN):(AArch64.PMUSERENR_EL0.CR):(AArch64.PMUSERENR_EL0.EN) == '000')
    //              || (!IsFeatureImplemented(FEAT_PMUv3p9) && (AArch64.PMUSERENR_EL0.CR):(AArch64.PMUSERENR_EL0.EN) == '00'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCCNTR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1' && PMUACR_EL1.C == '0')
    //         X<t,0x40> = Zeros(0x40);
    //     else
    //         X<t,0x40> = PMCCNTR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMCCNTR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCCNTR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMCCNTR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMCCNTR_EL0;
}


/**
 * PMXEVTYPER_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1101', 'op2': '001'})
 * Transformation status: 47 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMXEVTYPER_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (UInt(AArch64.PMSELR_EL0.SEL) != 0x1f && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersSelfHosted())
    {
        if (pGstFeats->fFgt)
            return iemRaiseUndefined(pVCpu);
        ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && UInt(AArch64.PMSELR_EL0.SEL) != 0x1f
            && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
        {
            if (!pGstFeats->fFgt)
                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
            else
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        }
        else if (   pGstFeats->fPmuV3p9
                 && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)
                 && (   (UInt(AArch64.PMSELR_EL0.SEL) != 0x1f && (AArch64.PMUACR_EL1)<UInt(AArch64.PMSELR_EL0.SEL)> == 0)
                     || (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f && !(iemCImplHlpGetPmUacrEl1(pVCpu) & RT_BIT_32(31)/*C*/))))
            *puDst = 0;
        else if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7),
                                         "PMCCFILTR_EL0",
                                         puDst,
                                         uInstrEssence);
        else
            *puDst = PMEVTYPER_EL0<UInt(AArch64.PMSELR_EL0.SEL)>;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && UInt(AArch64.PMSELR_EL0.SEL) != 0x1f
            && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
        {
            if (!pGstFeats->fFgt)
                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
            else
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        }
        else if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7),
                                         "PMCCFILTR_EL0",
                                         puDst,
                                         uInstrEssence);
        else
            *puDst = PMEVTYPER_EL0<UInt(AArch64.PMSELR_EL0.SEL)>;
    }
    else
    {
        if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7),
                                         "PMCCFILTR_EL0",
                                         puDst,
                                         uInstrEssence);
        *puDst = PMEVTYPER_EL0<UInt(AArch64.PMSELR_EL0.SEL)>;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (UInt(AArch64.PMSELR_EL0.SEL) != 0x1f && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersSelfHosted())
    //     if (IsFeatureImplemented(FEAT_FGT))
    //         Undefined()
    //     else
    //         ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMEVTYPERn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && UInt(AArch64.PMSELR_EL0.SEL) != 0x1f
    //              && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
    //         if (!IsFeatureImplemented(FEAT_FGT))
    //             ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_PMUv3p9)
    //              && PMUSERENR_EL0.UEN == '1'
    //              && (   (UInt(AArch64.PMSELR_EL0.SEL) != 0x1f && (AArch64.PMUACR_EL1)<UInt(AArch64.PMSELR_EL0.SEL)> == '0')
    //                  || (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f && AArch64.PMUACR_EL1.C == '0')))
    //         X<t,0x40> = Zeros(0x40);
    //     else if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
    //         X<t,0x40> = PMCCFILTR_EL0;
    //     else
    //         X<t,0x40> = PMEVTYPER_EL0<UInt(PMSELR_EL0.SEL)>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMEVTYPERn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && UInt(AArch64.PMSELR_EL0.SEL) != 0x1f
    //              && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
    //         if (!IsFeatureImplemented(FEAT_FGT))
    //             ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
    //         X<t,0x40> = PMCCFILTR_EL0;
    //     else
    //         X<t,0x40> = PMEVTYPER_EL0<UInt(PMSELR_EL0.SEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
    //         X<t,0x40> = PMCCFILTR_EL0;
    //     else
    //         X<t,0x40> = PMEVTYPER_EL0<UInt(PMSELR_EL0.SEL)>;
    // else if (PSTATE.EL == EL3)
    //     if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
    //         X<t,0x40> = PMCCFILTR_EL0;
    //     else
    //         X<t,0x40> = PMEVTYPER_EL0<UInt(PMSELR_EL0.SEL)>;
}


/**
 * PMXEVCNTR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1101', 'op2': '010'})
 * Transformation status: 31 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMXEVCNTR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersSelfHosted())
    {
        if (pGstFeats->fFgt)
            return iemRaiseUndefined(pVCpu);
        ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (pGstFeats->fPmuV3p9 && !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT64_C(0x19) /*UEN,ER,EN*/))
            || (!pGstFeats->fPmuV3p9 && !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT64_C(0x9) /*ER,EN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
        {
            if (!pGstFeats->fFgt)
                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
            else
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        }
        else if (   pGstFeats->fPmuV3p9
                 && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)
                 && (AArch64.PMUACR_EL1)<UInt(AArch64.PMSELR_EL0.SEL)> == 0)
            *puDst = 0;
        else
            *puDst = PMEVCNTR_EL0<UInt(AArch64.PMSELR_EL0.SEL)>;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
        {
            if (!pGstFeats->fFgt)
                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
            else
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        }
        else
            *puDst = PMEVCNTR_EL0<UInt(AArch64.PMSELR_EL0.SEL)>;
    }
    else
        *puDst = PMEVCNTR_EL0<UInt(AArch64.PMSELR_EL0.SEL)>;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersSelfHosted())
    //     if (IsFeatureImplemented(FEAT_FGT))
    //         Undefined()
    //     else
    //         ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   (   IsFeatureImplemented(FEAT_PMUv3p9)
    //                  && (AArch64.PMUSERENR_EL0.UEN):(AArch64.PMUSERENR_EL0.ER):(AArch64.PMUSERENR_EL0.EN) == '000')
    //              || (!IsFeatureImplemented(FEAT_PMUv3p9) && (AArch64.PMUSERENR_EL0.ER):(AArch64.PMUSERENR_EL0.EN) == '00'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMEVCNTRn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
    //         if (!IsFeatureImplemented(FEAT_FGT))
    //             ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_PMUv3p9)
    //              && PMUSERENR_EL0.UEN == '1'
    //              && (AArch64.PMUACR_EL1)<UInt(AArch64.PMSELR_EL0.SEL)> == '0')
    //         X<t,0x40> = Zeros(0x40);
    //     else
    //         X<t,0x40> = PMEVCNTR_EL0<UInt(PMSELR_EL0.SEL)>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMEVCNTRn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
    //         if (!IsFeatureImplemented(FEAT_FGT))
    //             ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMEVCNTR_EL0<UInt(PMSELR_EL0.SEL)>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMEVCNTR_EL0<UInt(PMSELR_EL0.SEL)>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMEVCNTR_EL0<UInt(PMSELR_EL0.SEL)>;
}


/**
 * PMUSERENR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMUSERENR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,0),
                                     "PMUSERENR_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,0),
                                     "PMUSERENR_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,0), "PMUSERENR_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMUSERENR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMUSERENR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMUSERENR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMUSERENR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMUSERENR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMUSERENR_EL0;
}


/**
 * PMOVSSET_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1110', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMOVSSET_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,3),
                                     "PMOVSSET_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,3),
                                     "PMOVSSET_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,3), "PMOVSSET_EL0", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMOVS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMOVSSET_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGRTR_EL2.PMOVS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMOVSSET_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMOVSSET_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMOVSSET_EL0;
}


/**
 * PMICNTR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMICNTR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3Icntr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fPmuV3p9 && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/) && AArch64.PMUACR_EL1.F0 == 0)
            *puDst = 0;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,4,0),
                                         "PMICNTR_EL0",
                                         puDst,
                                         uInstrEssence);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,4,0), "PMICNTR_EL0", puDst, uInstrEssence);
    }
    else
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,4,0), "PMICNTR_EL0", puDst, uInstrEssence);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3_ICNTR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.UEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMICNTR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1' && PMUACR_EL1.F0 == '0')
    //         X<t,0x40> = Zeros(0x40);
    //     else
    //         X<t,0x40> = PMICNTR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMICNTR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMICNTR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMICNTR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMICNTR_EL0;
}


/**
 * PMICFILTR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMICFILTR_EL0(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3Icntr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fPmuV3p9 && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/) && AArch64.PMUACR_EL1.F0 == 0)
            *puDst = 0;
        else
            return iemCImplA64_mrs_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,6,0),
                                         "PMICFILTR_EL0",
                                         puDst,
                                         uInstrEssence);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,6,0),
                                     "PMICFILTR_EL0",
                                     puDst,
                                     uInstrEssence);
    }
    else
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,6,0),
                                     "PMICFILTR_EL0",
                                     puDst,
                                     uInstrEssence);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3_ICNTR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.UEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMICFILTR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1' && PMUACR_EL1.F0 == '0')
    //         X<t,0x40> = Zeros(0x40);
    //     else
    //         X<t,0x40> = PMICFILTR_EL0;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMICFILTR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMICFILTR_EL0;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMICFILTR_EL0;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMICFILTR_EL0;
}


/**
 * VPIDR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0000', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VPIDR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x88, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.VPidrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x88>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = VPIDR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (!HaveEL(EL2))
    //         X<t,0x40> = MIDR_EL1;
    //     else
    //         X<t,0x40> = VPIDR_EL2;
}


/**
 * VMPIDR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0000', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VMPIDR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x50, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.VMpidrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x50>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = VMPIDR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (!HaveEL(EL2))
    //         X<t,0x40> = MPIDR_EL1;
    //     else
    //         X<t,0x40> = VMPIDR_EL2;
}


/**
 * SCTLR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.SctlrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = SCTLR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLR_EL2;
}


/**
 * ACTLR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ACTLR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,1), "ACTLR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = ACTLR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ACTLR_EL2;
}


/**
 * SCTLR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR2_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSctlr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,3), "SCTLR2_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SCTLR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SCTLR2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLR2_EL2;
}


/**
 * HCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x78, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.HcrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x78>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = HCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HCR_EL2;
}


/**
 * MDCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MDCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.MdcrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MDCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MDCR_EL2;
}


/**
 * CPTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CPTR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.CptrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = CPTR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CPTR_EL2;
}


/**
 * HSTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HSTR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x80, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,3), "HSTR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x80>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = HSTR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HSTR_EL2;
}


/**
 * HFGRTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HFGRTR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1b8, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = 0;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x1b8>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HFGRTR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HFGRTR_EL2;
}


/**
 * HFGWTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HFGWTR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1c0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = 0;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x1c0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HFGWTR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HFGWTR_EL2;
}


/**
 * HFGITR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HFGITR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1c8, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = 0;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x1c8>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HFGITR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HFGITR_EL2;
}


/**
 * HACR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HACR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,7), "HACR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = HACR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HACR_EL2;
}


/**
 * ZCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ZCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSve)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(8)/*TZ*/))
        return iemRaiseSystemAccessTrapSve(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 16) & UINT32_C(0x3)/*ZEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapSve(pVCpu, 2);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,0), "ZCR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SVE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.EZ == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.ZEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.EZ == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x19)
    //     else
    //         X<t,0x40> = ZCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.EZ == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x19)
    //     else
    //         X<t,0x40> = ZCR_EL2;
}


/**
 * TRFCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRFCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrf)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,1), "TRFCR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRF))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TTRF == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TTRF == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TRFCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TRFCR_EL2;
}


/**
 * HCRX_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HCRX_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fHcx)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0xa0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = 0;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_HCX))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0xa0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.HXEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.HXEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HCRX_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HCRX_EL2;
}


/**
 * TRCITECR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCITECR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fIte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,3), "TRCITECR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ITE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnITE == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnITE == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TRCITECR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TRCITECR_EL2;
}


/**
 * SMPRIMAP_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SMPRIMAP_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1f8, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,5), "SMPRIMAP_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x1f8>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SMPRIMAP_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SMPRIMAP_EL2;
}


/**
 * SMCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SMCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,6), "SMCR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         X<t,0x40> = SMCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         X<t,0x40> = SMCR_EL2;
}


/**
 * SDER32_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SDER32_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL2) && IsFeatureImplemented(FEAT_SEL2) && HaveAArch32EL(EL1)))
    //     Undefined()
    // else if (!HaveEL(EL2) || !IsFeatureImplemented(FEAT_SEL2) || !HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SDER32_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = SDER32_EL2;
}


/**
 * SCTLRMASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLRMASK_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,0), "SCTLRMASK_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SCTLRMASK_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLRMASK_EL2;
}


/**
 * ACTLRMASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ACTLRMASK_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,1), "ACTLRMASK_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ACTLRMASK_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ACTLRMASK_EL2;
}


/**
 * CPTRMASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CPTRMASK_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,2), "CPTRMASK_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = CPTRMASK_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CPTRMASK_EL2;
}


/**
 * SCTLR2MASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR2MASK_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,3), "SCTLR2MASK_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SCTLR2MASK_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLR2MASK_EL2;
}


/**
 * MAIR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MAIR2_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,1,1), "MAIR2_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MAIR2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MAIR2_EL2;
}


/**
 * MAIR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MAIR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.MairEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = MAIR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MAIR_EL2;
}


/**
 * PIRE0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PIRE0_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,2), "PIRE0_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PIRE0_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PIRE0_EL2;
}


/**
 * PIR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PIR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,3), "PIR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PIR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PIR_EL2;
}


/**
 * POR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_POR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Poe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,4), "POR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = POR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = POR_EL2;
}


/**
 * S2PIR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_S2PIR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS2Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x2b0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,5), "S2PIR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S2PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x2b0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = S2PIR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = S2PIR_EL2;
}


/**
 * AMAIR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMAIR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,0), "AMAIR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = AMAIR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMAIR_EL2;
}


/**
 * AMAIR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMAIR2_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,1), "AMAIR2_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = AMAIR2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMAIR2_EL2;
}


/**
 * MPAMHCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMHCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x930, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,4,0), "MPAMHCR_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x930>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMHCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMHCR_EL2;
}


/**
 * MPAMVPMV_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMVPMV_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x938, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,4,1), "MPAMVPMV_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x938>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMVPMV_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMVPMV_EL2;
}


/**
 * MPAM2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAM2_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,0), "MPAM2_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAM2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAM2_EL2;
}


/**
 * MPAMBW2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0101', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMBW2_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,4), "MPAMBW2_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMBW2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMBW2_EL2;
}


/**
 * MPAMBWCAP_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0101', 'op2': '110'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMBWCAP_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl || AArch64.MPAMIDR_EL1.HAS_HCR != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x910, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,6), "MPAMBWCAP_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) && AArch64.MPAMIDR_EL1.HAS_HCR == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x910>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMBWCAP_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMBWCAP_EL2;
}


/**
 * MPAMVPM0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMVPM0_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x940, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,0), "MPAMVPM0_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x940>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMVPM0_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMVPM0_EL2;
}


/**
 * MPAMVPM1_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMVPM1_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x948, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,1), "MPAMVPM1_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x948>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMVPM1_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMVPM1_EL2;
}


/**
 * MPAMVPM2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '010'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMVPM2_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x950, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,2), "MPAMVPM2_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x950>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMVPM2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMVPM2_EL2;
}


/**
 * MPAMVPM3_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '011'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMVPM3_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x958, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,3), "MPAMVPM3_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x958>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMVPM3_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMVPM3_EL2;
}


/**
 * MPAMVPM4_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '100'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMVPM4_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x960, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,4), "MPAMVPM4_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x960>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMVPM4_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMVPM4_EL2;
}


/**
 * MPAMVPM5_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMVPM5_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 4)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x968, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,5), "MPAMVPM5_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 4))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x968>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMVPM5_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMVPM5_EL2;
}


/**
 * MPAMVPM6_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '110'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMVPM6_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 5)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x970, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,6), "MPAMVPM6_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 5))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x970>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMVPM6_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMVPM6_EL2;
}


/**
 * MPAMVPM7_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '111'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMVPM7_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) != 7)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x978, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,7), "MPAMVPM7_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) == 7))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x978>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MPAMVPM7_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMVPM7_EL2;
}


/**
 * MECID_P0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MECID_P0_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MECID_P0_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MECID_P0_EL2;
}


/**
 * MECID_A0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MECID_A0_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MECID_A0_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MECID_A0_EL2;
}


/**
 * MECID_P1_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MECID_P1_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MECID_P1_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MECID_P1_EL2;
}


/**
 * MECID_A1_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MECID_A1_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = MECID_A1_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MECID_A1_EL2;
}


/**
 * MECIDR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MECIDR_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = MECIDR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MECIDR_EL2;
}


/**
 * VMECID_P_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VMECID_P_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = VMECID_P_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VMECID_P_EL2;
}


/**
 * VMECID_A_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VMECID_A_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = VMECID_A_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VMECID_A_EL2;
}


/**
 * VBAR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VBAR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.VBarEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = VBAR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VBAR_EL2;
}


/**
 * RVBAR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_RVBAR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1 && pGstFeats->fEl2 && (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 2 && pGstFeats->fEl2)
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,0,1), "RVBAR_EL2", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsHighestEL(EL2))
    //     Undefined()
    // else if (PSTATE.EL == EL1 && IsHighestEL(EL2) && EffectiveHCR_EL2_NVx() IN ('xx1'))
    //     AArch64_SystemAccessTrap(EL2, 0x18)
    // else if (PSTATE.EL == EL2 && IsHighestEL(EL2))
    //     X<t,0x40> = RVBAR_EL2;
    // else
    //     Undefined()
}


/**
 * RMR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_RMR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1 && pGstFeats->fEl2 && (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 2 && pGstFeats->fEl2)
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,0,2), "RMR_EL2", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsHighestEL(EL2))
    //     Undefined()
    // else if (PSTATE.EL == EL1 && IsHighestEL(EL2) && EffectiveHCR_EL2_NVx() IN ('xx1'))
    //     AArch64_SystemAccessTrap(EL2, 0x18)
    // else if (PSTATE.EL == EL2 && IsHighestEL(EL2))
    //     X<t,0x40> = RMR_EL2;
    // else
    //     Undefined()
}


/**
 * VDISR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VDISR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x500, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,1,1), "VDISR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x500>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = VDISR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VDISR_EL2;
}


/**
 * ICH_HCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1011', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICH_HCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3 || !pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x4c0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (AArch64.ICC_SRE_EL2.SRE == 0)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,0), "ICH_HCR_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x4c0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = ICH_HCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICH_HCR_EL2;
}


/**
 * ICH_VTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1011', 'op2': '001'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICH_VTR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3 || !pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (AArch64.ICC_SRE_EL2.SRE == 0)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,1), "ICH_VTR_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = ICH_VTR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICH_VTR_EL2;
}


/**
 * ICH_MISR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1011', 'op2': '010'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICH_MISR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3 || !pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (AArch64.ICC_SRE_EL2.SRE == 0)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,2), "ICH_MISR_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = ICH_MISR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICH_MISR_EL2;
}


/**
 * ICH_EISR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1011', 'op2': '011'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICH_EISR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3 || !pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (AArch64.ICC_SRE_EL2.SRE == 0)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,3), "ICH_EISR_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = ICH_EISR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICH_EISR_EL2;
}


/**
 * ICH_ELRSR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1011', 'op2': '101'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICH_ELRSR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3 || !pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (AArch64.ICC_SRE_EL2.SRE == 0)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,5), "ICH_ELRSR_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = ICH_ELRSR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICH_ELRSR_EL2;
}


/**
 * ICH_VMCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1011', 'op2': '111'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICH_VMCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3 || !pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x4c8, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (AArch64.ICC_SRE_EL2.SRE == 0)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,7), "ICH_VMCR_EL2", puDst, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x4c8>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         X<t,0x40> = ICH_VMCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICH_VMCR_EL2;
}


/**
 * ICC_SRE_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_SRE_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3 || !pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,9,5), "ICC_SRE_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.ICC_SRE_EL3.Enable == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.ICC_SRE_EL3.Enable == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_SRE_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else
    //         X<t,0x40> = ICC_SRE_EL2;
}


/**
 * CONTEXTIDR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1101', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CONTEXTIDR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fDebugV8p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,1), "CONTEXTIDR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_Debugv8p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CONTEXTIDR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CONTEXTIDR_EL2;
}


/**
 * TPIDR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1101', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TPIDR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x90, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.aTpIdr[2].u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x90>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = TPIDR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TPIDR_EL2;
}


/**
 * SCXTNUM_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1101', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCXTNUM_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fCvs2_2 && !pGstFeats->fCsv21p2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,7), "SCXTNUM_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_CSV2_2) || IsFeatureImplemented(FEAT_CSV2_1p2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = SCXTNUM_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCXTNUM_EL2;
}


/**
 * CNTVOFF_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTVOFF_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x60, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.CntVOffEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x60>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CNTVOFF_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTVOFF_EL2;
}


/**
 * CNTPOFF_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTPOFF_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEcvPOff)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1a8, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,0,6), "CNTPOFF_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_ECV_POFF))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x1a8>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ECVEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ECVEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = CNTPOFF_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTPOFF_EL2;
}


/**
 * CNTHCTL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHCTL_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.CntHCtlEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CNTHCTL_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTHCTL_EL2;
}


/**
 * CNTHP_TVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHP_TVAL_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (!(pVCpu->cpum.GstCtx.CntHpCtlEl2.u64 & UINT32_C(1)/*ENABLE*/))
        *puDst = 0;
    else
        *puDst = (uint64_t)(uint32_t)(pVCpu->cpum.GstCtx.CntHpCValEl2.u64 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) || (!HaveEL(EL3) && HaveEL(EL2) && !IsFeatureImplemented(FEAT_SEL2))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (CNTHP_CTL_EL2.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTHP_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    // else if (PSTATE.EL == EL3)
    //     if (CNTHP_CTL_EL2.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTHP_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
}


/**
 * CNTHP_CTL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHP_CTL_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.CntHpCtlEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) || (!HaveEL(EL3) && HaveEL(EL2) && !IsFeatureImplemented(FEAT_SEL2))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CNTHP_CTL_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTHP_CTL_EL2;
}


/**
 * CNTHP_CVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHP_CVAL_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.CntHpCValEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) || (!HaveEL(EL3) && HaveEL(EL2) && !IsFeatureImplemented(FEAT_SEL2))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CNTHP_CVAL_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTHP_CVAL_EL2;
}


/**
 * CNTHV_TVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 5 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHV_TVAL_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, puDst, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fVhe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (AArch64.CNTHV_CTL_EL2.ENABLE == 0)
        *puDst = 0;
    else
        *puDst = ZeroExtend((CNTHV_CVAL_EL2 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu))<[0x1f:0]>, 0x40);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_VHE) && (HaveEL(EL3) || (!HaveEL(EL3) && !IsFeatureImplemented(FEAT_SEL2)))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (CNTHV_CTL_EL2.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTHV_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    // else if (PSTATE.EL == EL3)
    //     if (CNTHV_CTL_EL2.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTHV_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
}


/**
 * CNTHV_CTL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHV_CTL_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fVhe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,1), "CNTHV_CTL_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_VHE) && (HaveEL(EL3) || (!HaveEL(EL3) && !IsFeatureImplemented(FEAT_SEL2)))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CNTHV_CTL_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTHV_CTL_EL2;
}


/**
 * CNTHV_CVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHV_CVAL_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fVhe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,2), "CNTHV_CVAL_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_VHE) && (HaveEL(EL3) || (!HaveEL(EL3) && !IsFeatureImplemented(FEAT_SEL2)))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = CNTHV_CVAL_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTHV_CVAL_EL2;
}


/**
 * CNTHVS_TVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHVS_TVAL_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_SEL2) && IsFeatureImplemented(FEAT_VHE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (CNTHVS_CTL_EL2.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTHVS_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else if (CNTHVS_CTL_EL2.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTHVS_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
}


/**
 * CNTHVS_CTL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHVS_CTL_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_SEL2) && IsFeatureImplemented(FEAT_VHE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         X<t,0x40> = CNTHVS_CTL_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = CNTHVS_CTL_EL2;
}


/**
 * CNTHVS_CVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHVS_CVAL_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_SEL2) && IsFeatureImplemented(FEAT_VHE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         X<t,0x40> = CNTHVS_CVAL_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = CNTHVS_CVAL_EL2;
}


/**
 * CNTHPS_TVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHPS_TVAL_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL2) && IsFeatureImplemented(FEAT_SEL2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (CNTHPS_CTL_EL2.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTHPS_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else if (CNTHPS_CTL_EL2.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTHPS_CVAL_EL2 - PhysicalCountInt())<[0x1f:0]>, 0x40);
}


/**
 * CNTHPS_CTL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHPS_CTL_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SEL2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         X<t,0x40> = CNTHPS_CTL_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = CNTHPS_CTL_EL2;
}


/**
 * CNTHPS_CVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0101', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTHPS_CVAL_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL2) && IsFeatureImplemented(FEAT_SEL2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         X<t,0x40> = CNTHPS_CVAL_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = CNTHPS_CVAL_EL2;
}


/**
 * TTBR0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TTBR0_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.Ttbr0El2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = TTBR0_EL2<[0x3f:0]>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TTBR0_EL2<[0x3f:0]>;
}


/**
 * TTBR1_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TTBR1_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fVhe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.Ttbr1El2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_VHE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = TTBR1_EL2<[0x3f:0]>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TTBR1_EL2<[0x3f:0]>;
}


/**
 * TCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.TcrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = TCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TCR_EL2;
}


/**
 * TCR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCR2_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTcr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,3), "TCR2_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TCR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TCR2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TCR2_EL2;
}


/**
 * VTTBR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VTTBR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x20, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.VTtbrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x20>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = VTTBR_EL2<[0x3f:0]>;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VTTBR_EL2<[0x3f:0]>;
}


/**
 * VTCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VTCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x40, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.VTcrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = VTCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VTCR_EL2;
}


/**
 * VNCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VNCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fNv2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0xb0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,2,0), "VNCR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_NV2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0xb0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = VNCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VNCR_EL2;
}


/**
 * HDBSSBR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HDBSSBR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fHdbss)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x2e0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,2), "HDBSSBR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_HDBSS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x2e0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.HDBSSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.HDBSSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HDBSSBR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HDBSSBR_EL2;
}


/**
 * HDBSSPROD_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HDBSSPROD_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fHdbss)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x300, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,3), "HDBSSPROD_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_HDBSS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x300>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.HDBSSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.HDBSSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HDBSSPROD_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HDBSSPROD_EL2;
}


/**
 * HACDBSBR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0011', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HACDBSBR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fHacdbs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x2f0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,4), "HACDBSBR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_HACDBS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x2f0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.HACDBSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.HACDBSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HACDBSBR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HACDBSBR_EL2;
}


/**
 * HACDBSCONS_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HACDBSCONS_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fHacdbs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x308, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,5), "HACDBSCONS_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_HACDBS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x308>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.HACDBSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.HACDBSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HACDBSCONS_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HACDBSCONS_EL2;
}


/**
 * GCSCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GCSCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = 0;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = GCSCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GCSCR_EL2;
}


/**
 * GCSPR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GCSPR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,5,1), "GCSPR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = GCSPR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GCSPR_EL2;
}


/**
 * VSTTBR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VSTTBR_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SEL2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x30>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         X<t,0x40> = VSTTBR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = VSTTBR_EL2;
}


/**
 * VSTCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0110', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VSTCR_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SEL2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x48>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         X<t,0x40> = VSTCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         X<t,0x40> = VSTCR_EL2;
}


/**
 * TCRMASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0111', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCRMASK_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,2), "TCRMASK_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TCRMASK_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TCRMASK_EL2;
}


/**
 * TCR2MASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCR2MASK_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,3), "TCR2MASK_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TCR2MASK_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TCR2MASK_EL2;
}


/**
 * DACR32_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_DACR32_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAa32El1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,0,0), "DACR32_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = DACR32_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = DACR32_EL2;
}


/**
 * HDFGRTR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HDFGRTR2_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x1a0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HDFGRTR2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HDFGRTR2_EL2;
}


/**
 * HDFGWTR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HDFGWTR2_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x1b0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HDFGWTR2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HDFGWTR2_EL2;
}


/**
 * HFGRTR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HFGRTR2_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x2c0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HFGRTR2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HFGRTR2_EL2;
}


/**
 * HFGWTR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HFGWTR2_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x2c8>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HFGWTR2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HFGWTR2_EL2;
}


/**
 * HDFGRTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HDFGRTR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1d0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = 0;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x1d0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HDFGRTR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HDFGRTR_EL2;
}


/**
 * HDFGWTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HDFGWTR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1d8, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = 0;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x1d8>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HDFGWTR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HDFGWTR_EL2;
}


/**
 * HAFGRTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HAFGRTR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1 || !pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1e8, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,6), "HAFGRTR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_AMUv1) && IsFeatureImplemented(FEAT_FGT)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x1e8>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HAFGRTR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HAFGRTR_EL2;
}


/**
 * HFGITR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HFGITR2_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x310>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = HFGITR2_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HFGITR2_EL2;
}


/**
 * SPSR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPSR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            *puDst = pVCpu->cpum.GstCtx.Spsr.u64;
        else if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        else
            return iemRaiseUndefined(pVCpu);
    }
    else
        *puDst = pVCpu->cpum.GstCtx.SpsrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = SPSR_EL1;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = SPSR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPSR_EL2;
}


/**
 * ELR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ELR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            *puDst = pVCpu->cpum.GstCtx.Elr.u64;
        else if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        else
            return iemRaiseUndefined(pVCpu);
    }
    else
        *puDst = pVCpu->cpum.GstCtx.ElrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = ELR_EL1;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = ELR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ELR_EL2;
}


/**
 * SP_EL1 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SP_EL1(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x240, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.aSpReg[1].u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x240>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = SP_EL1;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SP_EL1;
}


/**
 * SPSR_irq - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPSR_irq(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,0), "SPSR_irq", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = SPSR_irq;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPSR_irq;
}


/**
 * SPSR_abt - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPSR_abt(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,1), "SPSR_abt", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = SPSR_abt;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPSR_abt;
}


/**
 * SPSR_und - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPSR_und(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,2), "SPSR_und", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = SPSR_und;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPSR_und;
}


/**
 * SPSR_fiq - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPSR_fiq(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,3), "SPSR_fiq", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = SPSR_fiq;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPSR_fiq;
}


/**
 * IFSR32_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_IFSR32_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAa32El1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,0,1), "IFSR32_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = IFSR32_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = IFSR32_EL2;
}


/**
 * AFSR0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AFSR0_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,0), "AFSR0_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = AFSR0_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AFSR0_EL2;
}


/**
 * AFSR1_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AFSR1_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,1), "AFSR1_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = AFSR1_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AFSR1_EL2;
}


/**
 * ESR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ESR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            *puDst = pVCpu->cpum.GstCtx.Esr.u64;
        else if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        else
            return iemRaiseUndefined(pVCpu);
    }
    else
        *puDst = pVCpu->cpum.GstCtx.EsrEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = ESR_EL1;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = ESR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ESR_EL2;
}


/**
 * VSESR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VSESR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x508, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,2,3), "VSESR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = NVMem<0x508>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = VSESR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VSESR_EL2;
}


/**
 * FPEXC32_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_FPEXC32_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAa32El1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
        return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,3,0), "FPEXC32_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPEXC32_EL2;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TFP == '1')
    //         AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         X<t,0x40> = FPEXC32_EL2;
}


/**
 * TFSR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TFSR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
        {
            if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(56)/*ATA*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,0), "TFSR_EL1", puDst, uInstrEssence);
        }
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,6,0), "TFSR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //             Undefined()
    //         else if (EL2Enabled() && AArch64.HCR_EL2.ATA == '0')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = TFSR_EL1;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TFSR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TFSR_EL2;
}


/**
 * FAR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0110', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_FAR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            *puDst = pVCpu->cpum.GstCtx.Far.u64;
        else if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        else
            return iemRaiseUndefined(pVCpu);
    }
    else
        *puDst = pVCpu->cpum.GstCtx.FarEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         X<t,0x40> = FAR_EL1;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = FAR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = FAR_EL2;
}


/**
 * HPFAR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0110', 'CRm': '0000', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_HPFAR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    *puDst = pVCpu->cpum.GstCtx.HpFarEl2.u64;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     X<t,0x40> = HPFAR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = HPFAR_EL2;
}


/**
 * PFAR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0110', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PFAR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPfar)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,6,0,5), "PFAR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PFAR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PFAREn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PFAREn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PFAR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PFAR_EL2;
}


/**
 * PMBSR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1001', 'CRm': '1010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMBSR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpeExc)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,10,3), "PMBSR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE_EXC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.PMSEE == '00')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.PMSEE == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMBSR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMBSR_EL2;
}


/**
 * TRBSR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1001', 'CRm': '1011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRBSR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbeExc)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,11,3), "TRBSR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE_EXC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TRBEE == '00')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TRBEE == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = TRBSR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TRBSR_EL2;
}


/**
 * PMSCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1001', 'CRm': '1001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSCR_EL2(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,9,0), "PMSCR_EL2", puDst, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = PMSCR_EL2;
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMSCR_EL2;
}


/**
 * SCTLR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x110, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Sctlr.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x110>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SCTLR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SCTLR_EL1;
    //     else
    //         Undefined()
}


/**
 * ACTLR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ACTLR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x118, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Actlr.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x118>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = ACTLR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = ACTLR_EL1;
    //     else
    //         Undefined()
}


/**
 * CPACR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CPACR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x100, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Cpacr.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x100>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = CPACR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CPACR_EL1;
    //     else
    //         Undefined()
}


/**
 * SCTLR2_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR2_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSctlr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x278, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3), "SCTLR2_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SCTLR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x278>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = SCTLR2_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SCTLR2_EL1;
    //     else
    //         Undefined()
}


/**
 * ZCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ZCR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSve)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1e0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if ((((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 16) & UINT32_C(0x3)/*ZEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSve(pVCpu, 2);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,0), "ZCR_EL1", puDst, uInstrEssence);
    }
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SVE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x1e0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.EZ == '0')
    //             Undefined()
    //         else if (AArch64.CPTR_EL2.ZEN IN 'x0')
    //             AArch64_SystemAccessTrap(EL2, 0x19)
    //         else if (HaveEL(EL3) && AArch64.CPTR_EL3.EZ == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x19)
    //         else
    //             X<t,0x40> = ZCR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         if (AArch64.CPTR_EL3.EZ == '0')
    //             AArch64_SystemAccessTrap(EL3, 0x19)
    //         else
    //             X<t,0x40> = ZCR_EL1;
    //     else
    //         Undefined()
}


/**
 * TRFCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRFCR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrf)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x880, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,1), "TRFCR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRF))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x880>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TTRF == '1')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MDCR_EL3.TTRF == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = TRFCR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TRFCR_EL1;
    //     else
    //         Undefined()
}


/**
 * TRCITECR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRCITECR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fIte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x888, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,3), "TRCITECR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ITE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x888>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnITE == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnITE == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = TRCITECR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TRCITECR_EL1;
    //     else
    //         Undefined()
}


/**
 * SMCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SMCR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x1f0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if ((((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,6), "SMCR_EL1", puDst, uInstrEssence);
    }
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x1f0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //             Undefined()
    //         else if (AArch64.CPTR_EL2.SMEN IN 'x0')
    //             AArch64_SystemAccessTrap(EL2, 0x1d)
    //         else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x1d)
    //         else
    //             X<t,0x40> = SMCR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         if (AArch64.CPTR_EL3.ESM == '0')
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //         else
    //             X<t,0x40> = SMCR_EL1;
    //     else
    //         Undefined()
}


/**
 * SCTLRMASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLRMASK_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x318, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,0),
                                     "SCTLRMASK_EL1",
                                     puDst,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x318>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = SCTLRMASK_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SCTLRMASK_EL1;
    //     else
    //         Undefined()
}


/**
 * ACTLRMASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ACTLRMASK_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x340, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,1),
                                     "ACTLRMASK_EL1",
                                     puDst,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x340>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = ACTLRMASK_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = ACTLRMASK_EL1;
    //     else
    //         Undefined()
}


/**
 * CPACRMASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CPACRMASK_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x320, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,2),
                                     "CPACRMASK_EL1",
                                     puDst,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x320>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = CPACRMASK_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CPACRMASK_EL1;
    //     else
    //         Undefined()
}


/**
 * SCTLR2MASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR2MASK_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x328, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,3),
                                     "SCTLR2MASK_EL1",
                                     puDst,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x328>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = SCTLR2MASK_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SCTLR2MASK_EL1;
    //     else
    //         Undefined()
}


/**
 * MAIR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MAIR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x140, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Mair.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x140>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = MAIR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = MAIR_EL1;
    //     else
    //         Undefined()
}


/**
 * MAIR2_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MAIR2_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x280, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,1), "MAIR2_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x280>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = MAIR2_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = MAIR2_EL1;
    //     else
    //         Undefined()
}


/**
 * PIRE0_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PIRE0_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x290, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,2), "PIRE0_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x290>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = PIRE0_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = PIRE0_EL1;
    //     else
    //         Undefined()
}


/**
 * PIR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PIR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x2a0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,3), "PIR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x2a0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = PIR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = PIR_EL1;
    //     else
    //         Undefined()
}


/**
 * POR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_POR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Poe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x2a8, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,4), "POR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x2a8>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = POR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = POR_EL1;
    //     else
    //         Undefined()
}


/**
 * AMAIR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMAIR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x148, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Amair.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x148>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = AMAIR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = AMAIR_EL1;
    //     else
    //         Undefined()
}


/**
 * AMAIR2_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMAIR2_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x288, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,3,1), "AMAIR2_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x288>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = AMAIR2_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = AMAIR2_EL1;
    //     else
    //         Undefined()
}


/**
 * MPAM1_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAM1_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x900, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,0), "MPAM1_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x900>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = MPAM1_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = MPAM1_EL1;
    //     else
    //         Undefined()
}


/**
 * MPAMBW1_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0101', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMBW1_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x908, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,4), "MPAMBW1_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x908>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             Undefined()
    //         else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = MPAMBW1_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = MPAMBW1_EL1;
    //     else
    //         Undefined()
}


/**
 * VBAR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VBAR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x250, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.VBar.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x250>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = VBAR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = VBAR_EL1;
    //     else
    //         Undefined()
}


/**
 * CONTEXTIDR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1101', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CONTEXTIDR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x108, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.ContextIdr.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x108>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CONTEXTIDR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CONTEXTIDR_EL1;
    //     else
    //         Undefined()
}


/**
 * SCXTNUM_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1101', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCXTNUM_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fCvs2_2 && !pGstFeats->fCsv21p2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x188, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,7), "SCXTNUM_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_CSV2_2) || IsFeatureImplemented(FEAT_CSV2_1p2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x188>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = SCXTNUM_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SCXTNUM_EL1;
    //     else
    //         Undefined()
}


/**
 * CNTKCTL_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTKCTL_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.CntKCtl.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CNTKCTL_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CNTKCTL_EL1;
    //     else
    //         Undefined()
}


/**
 * CNTP_TVAL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTP_TVAL_EL02(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = 0;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (CNTP_CTL_EL0.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTP_CVAL_EL0 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         if (CNTP_CTL_EL0.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTP_CVAL_EL0 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    //     else
    //         Undefined()
}


/**
 * CNTP_CTL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTP_CTL_EL02(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
        {
            if (   pGstFeats->fEl2
                && (   !pGstFeats->fVhe
                    || !pGstFeats->fEl2
                    || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                    || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(15)/*EL1NVPCT*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemCImplHlpNVMemReadU64(pVCpu, 0x180, puDst);
        }
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = 0;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL1NVPCT == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             X<t,0x40> = NVMem<0x180>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CNTP_CTL_EL0;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CNTP_CTL_EL0;
    //     else
    //         Undefined()
}


/**
 * CNTP_CVAL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTP_CVAL_EL02(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
        {
            if (   pGstFeats->fEl2
                && (   !pGstFeats->fVhe
                    || !pGstFeats->fEl2
                    || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                    || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(15)/*EL1NVPCT*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemCImplHlpNVMemReadU64(pVCpu, 0x178, puDst);
        }
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                     "CNTP_CVAL_EL0",
                                     puDst,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL1NVPCT == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             X<t,0x40> = NVMem<0x178>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CNTP_CVAL_EL0;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CNTP_CVAL_EL0;
    //     else
    //         Undefined()
}


/**
 * CNTV_TVAL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTV_TVAL_EL02(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if (!(pVCpu->cpum.GstCtx.CntvCtlEl0 & UINT32_C(1)/*ENABLE*/))
            *puDst = 0;
        else
            *puDst = (uint64_t)(uint32_t)(pVCpu->cpum.GstCtx.CntvCValEl0 - iemCImplHlpGetPhysicalSystemTimerCount(pVCpu) - pVCpu->cpum.GstCtx.CntVOffEl2.u64);
    }
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (CNTV_CTL_EL0.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTV_CVAL_EL0 - PhysicalCountInt() - CNTVOFF_EL2)<[0x1f:0]>, 0x40);
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         if (CNTV_CTL_EL0.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTV_CVAL_EL0 - PhysicalCountInt() - CNTVOFF_EL2)<[0x1f:0]>, 0x40);
    //     else
    //         Undefined()
}


/**
 * CNTV_CTL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTV_CTL_EL02(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
        {
            if (   pGstFeats->fEl2
                && (   !pGstFeats->fVhe
                    || !pGstFeats->fEl2
                    || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                    || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(16)/*EL1NVVCT*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemCImplHlpNVMemReadU64(pVCpu, 0x170, puDst);
        }
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.CntvCtlEl0;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL1NVVCT == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             X<t,0x40> = NVMem<0x170>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CNTV_CTL_EL0;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CNTV_CTL_EL0;
    //     else
    //         Undefined()
}


/**
 * CNTV_CVAL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTV_CVAL_EL02(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
        {
            if (   pGstFeats->fEl2
                && (   !pGstFeats->fVhe
                    || !pGstFeats->fEl2
                    || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                    || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(16)/*EL1NVVCT*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemCImplHlpNVMemReadU64(pVCpu, 0x168, puDst);
        }
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.CntvCValEl0;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL1NVVCT == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             X<t,0x40> = NVMem<0x168>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CNTV_CVAL_EL0;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = CNTV_CVAL_EL0;
    //     else
    //         Undefined()
}


/**
 * TTBR0_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TTBR0_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x200, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Ttbr0.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x200>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TTBR0_EL1<[0x3f:0]>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TTBR0_EL1<[0x3f:0]>;
    //     else
    //         Undefined()
}


/**
 * TTBR1_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TTBR1_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x210, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Ttbr1.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x210>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TTBR1_EL1<[0x3f:0]>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TTBR1_EL1<[0x3f:0]>;
    //     else
    //         Undefined()
}


/**
 * TCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x120, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Tcr.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x120>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TCR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TCR_EL1;
    //     else
    //         Undefined()
}


/**
 * TCR2_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCR2_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTcr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x270, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3), "TCR2_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TCR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x270>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = TCR2_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TCR2_EL1;
    //     else
    //         Undefined()
}


/**
 * GCSCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GCSCR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x8d0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = 0;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x8d0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = GCSCR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = GCSCR_EL1;
    //     else
    //         Undefined()
}


/**
 * GCSPR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GCSPR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x8c0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,1), "GCSPR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x8c0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = GCSPR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = GCSPR_EL1;
    //     else
    //         Undefined()
}


/**
 * TCRMASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0111', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCRMASK_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x330, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,2), "TCRMASK_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x330>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = TCRMASK_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TCRMASK_EL1;
    //     else
    //         Undefined()
}


/**
 * TCR2MASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCR2MASK_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x338, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,3), "TCR2MASK_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x338>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = TCR2MASK_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TCR2MASK_EL1;
    //     else
    //         Undefined()
}


/**
 * SPSR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPSR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x160, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Spsr.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x160>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SPSR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = SPSR_EL1;
    //     else
    //         Undefined()
}


/**
 * ELR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0100', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ELR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x230, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Elr.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x230>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = ELR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = ELR_EL1;
    //     else
    //         Undefined()
}


/**
 * AFSR0_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0101', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AFSR0_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x128, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Afsr0.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x128>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = AFSR0_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = AFSR0_EL1;
    //     else
    //         Undefined()
}


/**
 * AFSR1_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0101', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AFSR1_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x130, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Afsr1.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x130>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = AFSR1_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = AFSR1_EL1;
    //     else
    //         Undefined()
}


/**
 * ESR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0101', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ESR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x138, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Esr.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x138>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = ESR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = ESR_EL1;
    //     else
    //         Undefined()
}


/**
 * TFSR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0101', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TFSR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x190, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,0), "TFSR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x190>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = TFSR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = TFSR_EL1;
    //     else
    //         Undefined()
}


/**
 * FAR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0110', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_FAR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x220, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = pVCpu->cpum.GstCtx.Far.u64;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x220>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = FAR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = FAR_EL1;
    //     else
    //         Undefined()
}


/**
 * PFAR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0110', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PFAR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPfar)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x2d0, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,6,0,5), "PFAR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PFAR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x2d0>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PFAREn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.PFAREn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = PFAR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = PFAR_EL1;
    //     else
    //         Undefined()
}


/**
 * PMBSR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1001', 'CRm': '1010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMBSR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x820, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,3), "PMBSR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x820>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (   HaveEL(EL3)
    //             && EL3SDDUndefPriority()
    //             && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                 || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                 || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //             Undefined()
    //         else if (   HaveEL(EL3)
    //                  && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                      || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                      || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = PMBSR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = PMBSR_EL1;
    //     else
    //         Undefined()
}


/**
 * TRBSR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1001', 'CRm': '1011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRBSR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbeExc)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x860, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_mrs_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,3), "TRBSR_EL1", puDst, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE_EXC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x860>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (   HaveEL(EL3)
    //             && EL3SDDUndefPriority()
    //             && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                 || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                 || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //             Undefined()
    //         else if (   HaveEL(EL3)
    //                  && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                      || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                      || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (   IsFeatureImplemented(FEAT_TRBE_EXT)
    //                  && AArch64.OSLSR_EL1.OSLK == '0'
    //                  && HaltingAllowed()
    //                  && ext.EDSCR2.TTA == '1')
    //             Halt(DebugHalt_SoftwareAccess)
    //         else
    //             X<t,0x40> = TRBSR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         if (   IsFeatureImplemented(FEAT_TRBE_EXT)
    //             && AArch64.OSLSR_EL1.OSLK == '0'
    //             && HaltingAllowed()
    //             && ext.EDSCR2.TTA == '1')
    //             Halt(DebugHalt_SoftwareAccess)
    //         else
    //             X<t,0x40> = TRBSR_EL1;
    //     else
    //         Undefined()
}


/**
 * PMSCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1001', 'CRm': '1001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMSCR_EL12(PVMCPU pVCpu, uint64_t * puDst, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemReadU64(pVCpu, 0x828, puDst);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        *puDst = 0;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         X<t,0x40> = NVMem<0x828>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (   HaveEL(EL3)
    //             && EL3SDDUndefPriority()
    //             && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                 || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                 || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //             Undefined()
    //         else if (   HaveEL(EL3)
    //                  && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                      || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                      || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = PMSCR_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         X<t,0x40> = PMSCR_EL1;
    //     else
    //         Undefined()
}


/**
 * SCTLR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLR_EL3;
}


/**
 * ACTLR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ACTLR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ACTLR_EL3;
}


/**
 * SCTLR2_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCTLR2_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SCTLR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCTLR2_EL3;
}


/**
 * SCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCR_EL3;
}


/**
 * SDER32_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SDER32_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) && HaveAArch32EL(EL1)))
    //     Undefined()
    // else if (!HaveEL(EL3) || !HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SDER32_EL3;
}


/**
 * CPTR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CPTR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CPTR_EL3;
}


/**
 * FGWTE3_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_FGWTE3_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) && IsFeatureImplemented(FEAT_FGWTE3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = FGWTE3_EL3;
}


/**
 * ZCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ZCR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SVE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.EZ == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x19)
    //     else
    //         X<t,0x40> = ZCR_EL3;
}


/**
 * SMCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SMCR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_SME) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         X<t,0x40> = SMCR_EL3;
}


/**
 * MDCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MDCR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MDCR_EL3;
}


/**
 * MAIR2_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MAIR2_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MAIR2_EL3;
}


/**
 * MECID_RL_A_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '1010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MECID_RL_A_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MECID_RL_A_EL3;
}


/**
 * MAIR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MAIR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MAIR_EL3;
}


/**
 * PIR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PIR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PIR_EL3;
}


/**
 * POR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_POR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = POR_EL3;
}


/**
 * AMAIR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMAIR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMAIR_EL3;
}


/**
 * AMAIR2_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AMAIR2_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AMAIR2_EL3;
}


/**
 * MPAM3_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAM3_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAM3_EL3;
}


/**
 * MPAMBW3_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0101', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MPAMBW3_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MPAMBW3_EL3;
}


/**
 * VBAR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VBAR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VBAR_EL3;
}


/**
 * RVBAR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_RVBAR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL3 && IsHighestEL(EL3))
    //     X<t,0x40> = RVBAR_EL3;
    // else
    //     Undefined()
}


/**
 * RMR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_RMR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL3 && IsHighestEL(EL3))
    //     X<t,0x40> = RMR_EL3;
    // else
    //     Undefined()
}


/**
 * VDISR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VDISR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_E3DSE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VDISR_EL3;
}


/**
 * ICC_CTLR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '1100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_CTLR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_CTLR_EL3;
}


/**
 * ICC_SRE_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '1100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_SRE_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ICC_SRE_EL3;
}


/**
 * ICC_IGRPEN1_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '1100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ICC_IGRPEN1_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         X<t,0x40> = ICC_IGRPEN1_EL3;
}


/**
 * TPIDR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1101', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TPIDR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TPIDR_EL3;
}


/**
 * SCXTNUM_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1101', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SCXTNUM_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) && (IsFeatureImplemented(FEAT_CSV2_2) || IsFeatureImplemented(FEAT_CSV2_1p2))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SCXTNUM_EL3;
}


/**
 * TTBR0_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TTBR0_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TTBR0_EL3;
}


/**
 * TCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TCR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TCR_EL3;
}


/**
 * GPTBR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GPTBR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GPTBR_EL3;
}


/**
 * GPCBW_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GPCBW_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME_GPC3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GPCBW_EL3;
}


/**
 * GPCCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GPCCR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GPCCR_EL3;
}


/**
 * GCSCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GCSCR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GCS) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GCSCR_EL3;
}


/**
 * GCSPR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_GCSPR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GCS) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = GCSPR_EL3;
}


/**
 * SPSR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SPSR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SPSR_EL3;
}


/**
 * ELR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0100', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ELR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ELR_EL3;
}


/**
 * SP_EL2 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0100', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_SP_EL2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = SP_EL2;
}


/**
 * AFSR0_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0101', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AFSR0_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AFSR0_EL3;
}


/**
 * AFSR1_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0101', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_AFSR1_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = AFSR1_EL3;
}


/**
 * ESR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0101', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_ESR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = ESR_EL3;
}


/**
 * VSESR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0101', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_VSESR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_E3DSE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = VSESR_EL3;
}


/**
 * TFSR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0101', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TFSR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TFSR_EL3;
}


/**
 * FAR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0110', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_FAR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = FAR_EL3;
}


/**
 * MFAR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0110', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_MFAR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_PFAR) || IsFeatureImplemented(FEAT_RME)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = MFAR_EL3;
}


/**
 * PMBSR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1001', 'CRm': '1010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_PMBSR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_SPE_EXC) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = PMBSR_EL3;
}


/**
 * TRBSR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1001', 'CRm': '1011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_TRBSR_EL3(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TRBE_EXC) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = TRBSR_EL3;
}


/**
 * CNTPS_TVAL_EL1 - OrderedDict({'op0': '11', 'op1': '111', 'CRn': '1110', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTPS_TVAL_EL1(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ST == '0')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.EEL2 == '1')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.ST == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (CNTPS_CTL_EL1.ENABLE == '0')
    //             X<t,0x40> = (bits(0x40)) UNKNOWN;
    //         else
    //             X<t,0x40> = ZeroExtend((CNTPS_CVAL_EL1 - PhysicalCountInt())<[0x1f:0]>, 0x40);
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (CNTPS_CTL_EL1.ENABLE == '0')
    //         X<t,0x40> = (bits(0x40)) UNKNOWN;
    //     else
    //         X<t,0x40> = ZeroExtend((CNTPS_CVAL_EL1 - PhysicalCountInt())<[0x1f:0]>, 0x40);
}


/**
 * CNTPS_CTL_EL1 - OrderedDict({'op0': '11', 'op1': '111', 'CRn': '1110', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTPS_CTL_EL1(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ST == '0')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.EEL2 == '1')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.ST == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = CNTPS_CTL_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTPS_CTL_EL1;
}


/**
 * CNTPS_CVAL_EL1 - OrderedDict({'op0': '11', 'op1': '111', 'CRn': '1110', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_mrs_CNTPS_CVAL_EL1(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    RT_NOREF(puDst);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ST == '0')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.EEL2 == '1')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.ST == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             X<t,0x40> = CNTPS_CVAL_EL1;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     X<t,0x40> = CNTPS_CVAL_EL1;
}

// DBGBVR<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': (m)[0:3], 'op2': '100'})
//    if (   (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_BREAKPOINTS)
    //    || (IsFeatureImplemented(FEAT_Debugv8p9) && m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10 >= NUM_BREAKPOINTS))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.DBGBVRn_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGBVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGBVR_EL1<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGBVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGBVR_EL1<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGBVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGBVR_EL1<m>;

// DBGBCR<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': (m)[0:3], 'op2': '101'})
//    if (   (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_BREAKPOINTS)
    //    || (IsFeatureImplemented(FEAT_Debugv8p9) && m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10 >= NUM_BREAKPOINTS))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.DBGBCRn_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGBCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGBCR_EL1<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGBCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGBCR_EL1<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGBCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGBCR_EL1<m>;

// DBGWVR<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': (m)[0:3], 'op2': '110'})
//    if (   (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_WATCHPOINTS)
    //    || (IsFeatureImplemented(FEAT_Debugv8p9) && m + UInt(AArch64.MDSELR_EL1.BANK) * 0x10 >= NUM_WATCHPOINTS))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.DBGWVRn_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGWVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGWVR_EL1<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGWVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGWVR_EL1<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGWVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGWVR_EL1<m>;

// DBGWCR<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': (m)[0:3], 'op2': '111'})
//    if (   (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_WATCHPOINTS)
    //    || (IsFeatureImplemented(FEAT_Debugv8p9) && m + UInt(AArch64.MDSELR_EL1.BANK) * 0x10 >= NUM_WATCHPOINTS))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.DBGWCRn_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGWCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGWCR_EL1<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGWCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGWCR_EL1<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            X<t,0x40> = DBGWCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10>;
//        else
//            X<t,0x40> = DBGWCR_EL1<m>;

// SPMCGCR<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1001', 'CRm': '1101', 'op2': '00'})
//    if (!IsFeatureImplemented(FEAT_SPMU))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMID == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = SPMCGCR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL),m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = SPMCGCR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL),m>;
//    else if (PSTATE.EL == EL3)
//        X<t,0x40> = SPMCGCR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL),m>;

// PMEVCNTSVR<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1110', 'CRm': '10', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_PMUv3_SS))
//        Undefined()
//    else if (m >= GetNumEventCountersSelfHosted())
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSS == '0')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nPMSSDATA == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && m >= GetNumEventCountersAccessible())
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSS == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = PMEVCNTSVR_EL1<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSS == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSS == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = PMEVCNTSVR_EL1<m>;
//    else if (PSTATE.EL == EL3)
//        X<t,0x40> = PMEVCNTSVR_EL1<m>;

// TRCIMSPEC<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0', 'op2': '111'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRCIMSPECn == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCIMSPEC<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCIMSPEC<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCIMSPEC<m>;

// TRCSEQEVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '00', 'op2': '100'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSEQEVR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSEQEVR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSEQEVR<m>;

// TRCCNTRLDVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '00', 'op2': '101'})
//    if (m >= NUM_TRACE_COUNTERS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCNTRLDVR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCNTRLDVR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCNTRLDVR<m>;

// TRCCNTCTLR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '01', 'op2': '101'})
//    if (m >= NUM_TRACE_COUNTERS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCNTCTLR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCNTCTLR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCNTCTLR<m>;

// TRCEXTINSELR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '10', 'op2': '100'})
//    if (m >= NUM_TRACE_EXTERNAL_INPUT_SELECTOR_RESOURCES)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCEXTINSELR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCEXTINSELR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCEXTINSELR<m>;

// TRCCNTVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '10', 'op2': '101'})
//    if (m >= NUM_TRACE_COUNTERS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRCCNTVRn == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCNTVR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCNTVR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCNTVR<m>;

// TRCSSCCR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0001', 'CRm': '0', 'op2': '010'})
//    if (m >= NUM_TRACE_SINGLE_SHOT_COMPARATOR_CONTROLS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSSCCR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSSCCR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSSCCR<m>;

// TRCSSPCICR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0001', 'CRm': '0', 'op2': '011'})
//    if (m >= NUM_TRACE_SINGLE_SHOT_COMPARATOR_CONTROLS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSSPCICR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSSPCICR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSSPCICR<m>;

// TRCSSCSR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0001', 'CRm': '1', 'op2': '010'})
//    if (m >= NUM_TRACE_SINGLE_SHOT_COMPARATOR_CONTROLS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRCSSCSRn == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSSCSR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSSCSR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCSSCSR<m>;

// TRCRSCTLR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0001', 'CRm': (m)[0:3], 'op2': '00'})
//    if (m >= NUM_TRACE_RESOURCE_SELECTOR_PAIRS * 2)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCRSCTLR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCRSCTLR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCRSCTLR<m>;

// TRCACVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0010', 'CRm': '0', 'op2': '00'})
//    if (m >= NUM_TRACE_ADDRESS_COMPARATOR_PAIRS * 2)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCACVR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCACVR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCACVR<m>;

// TRCACATR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0010', 'CRm': '0', 'op2': '01'})
//    if (m >= NUM_TRACE_ADDRESS_COMPARATOR_PAIRS * 2)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCACATR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCACATR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCACATR<m>;

// TRCCIDCVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0', 'op2': '000'})
//    if (m >= NUM_TRACE_CONTEXT_IDENTIFIER_COMPARATORS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCIDCVR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCIDCVR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCCIDCVR<m>;

// TRCVMIDCVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0', 'op2': '001'})
//    if (m >= NUM_TRACE_VIRTUAL_CONTEXT_IDENTIFIER_COMPARATORS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCVMIDCVR<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCVMIDCVR<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            X<t,0x40> = TRCVMIDCVR<m>;

// BRBINF<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1000', 'CRm': (m)[0:3], 'op2': '00'})
//    if (!IsFeatureImplemented(FEAT_BRBE))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.nBRBDATA == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (m + UInt(AArch64.BRBFCR_EL1.BANK) * 0x20 >= NUM_BRBE_RECORDS)
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = BRBINF_EL1<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (m + UInt(AArch64.BRBFCR_EL1.BANK) * 0x20 >= NUM_BRBE_RECORDS)
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = BRBINF_EL1<m>;
//    else if (PSTATE.EL == EL3)
//        if (m + UInt(AArch64.BRBFCR_EL1.BANK) * 0x20 >= NUM_BRBE_RECORDS)
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = BRBINF_EL1<m>;

// BRBSRC<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1000', 'CRm': (m)[0:3], 'op2': '01'})
//    if (!IsFeatureImplemented(FEAT_BRBE))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.nBRBDATA == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (m + UInt(AArch64.BRBFCR_EL1.BANK) * 0x20 >= NUM_BRBE_RECORDS)
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = BRBSRC_EL1<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (m + UInt(AArch64.BRBFCR_EL1.BANK) * 0x20 >= NUM_BRBE_RECORDS)
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = BRBSRC_EL1<m>;
//    else if (PSTATE.EL == EL3)
//        if (m + UInt(AArch64.BRBFCR_EL1.BANK) * 0x20 >= NUM_BRBE_RECORDS)
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = BRBSRC_EL1<m>;

// BRBTGT<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1000', 'CRm': (m)[0:3], 'op2': '10'})
//    if (!IsFeatureImplemented(FEAT_BRBE))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.nBRBDATA == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (m + UInt(BRBFCR_EL1.BANK) * 0x20 >= NUM_BRBE_RECORDS)
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = BRBTGT_EL1<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (m + UInt(BRBFCR_EL1.BANK) * 0x20 >= NUM_BRBE_RECORDS)
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = BRBTGT_EL1<m>;
//    else if (PSTATE.EL == EL3)
//        if (m + UInt(BRBFCR_EL1.BANK) * 0x20 >= NUM_BRBE_RECORDS)
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = BRBTGT_EL1<m>;

// SPMEVCNTR<m>_EL0
// encoding=OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1110', 'CRm': '000', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_SPMU))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (AArch64.MDSCR_EL1.EnSPM == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   !ELIsInHost(EL0)
         //        &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMEVCNTRn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVCNTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMEVCNTRn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVCNTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVCNTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL3)
//        if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVCNTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;

// SPMEVTYPER<m>_EL0
// encoding=OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1110', 'CRm': '001', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_SPMU))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (AArch64.MDSCR_EL1.EnSPM == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   !ELIsInHost(EL0)
         //        &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVTYPER_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVTYPER_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVTYPER_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL3)
//        if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVTYPER_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;

// SPMEVFILTR<m>_EL0
// encoding=OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1110', 'CRm': '010', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_SPMU))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (AArch64.MDSCR_EL1.EnSPM == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   !ELIsInHost(EL0)
         //        &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVFILTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVFILTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVFILTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL3)
//        if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVFILTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;

// SPMEVFILT2R<m>_EL0
// encoding=OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1110', 'CRm': '011', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_SPMU))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (AArch64.MDSCR_EL1.EnSPM == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   !ELIsInHost(EL0)
         //        &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVFILT2R_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGRTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVFILT2R_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           == '00')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVFILT2R_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;
//    else if (PSTATE.EL == EL3)
//        if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = SPMEVFILT2R_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m>;

// ICC_AP0R<m>_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1000', 'op2': '1'})
//    if (!IsFeatureImplemented(FEAT_GICv3))
//        Undefined()
//    else if (m == 1 && NUM_GIC_PRIORITY_BITS < 6)
//        Undefined()
//    else if ((m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
//            Undefined()
//        else if (AArch64.ICC_SRE_EL1.SRE == '0')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
//            X<t,0x40> = ICV_AP0R_EL1<m>;
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = ICC_AP0R_EL1<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
//            Undefined()
//        else if (AArch64.ICC_SRE_EL2.SRE == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = ICC_AP0R_EL1<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.ICC_SRE_EL3.SRE == '0')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = ICC_AP0R_EL1<m>;

// ICC_AP1R<m>_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1001', 'op2': '0'})
//    if (!IsFeatureImplemented(FEAT_GICv3))
//        Undefined()
//    else if (m == 1 && NUM_GIC_PRIORITY_BITS < 6)
//        Undefined()
//    else if ((m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
//            Undefined()
//        else if (AArch64.ICC_SRE_EL1.SRE == '0')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
//            X<t,0x40> = ICV_AP1R_EL1<m>;
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3))
//            if (AArch64.SCR_EL3.NS == '0')
//                X<t,0x40> = ICC_AP1R_EL1_S<m>;
//            else
//                X<t,0x40> = ICC_AP1R_EL1_NS<m>;
//        else
//            X<t,0x40> = ICC_AP1R_EL1<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
//            Undefined()
//        else if (AArch64.ICC_SRE_EL2.SRE == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3))
//            if (AArch64.SCR_EL3.NS == '0')
//                X<t,0x40> = ICC_AP1R_EL1_S<m>;
//            else
//                X<t,0x40> = ICC_AP1R_EL1_NS<m>;
//        else
//            X<t,0x40> = ICC_AP1R_EL1<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.ICC_SRE_EL3.SRE == '0')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.SCR_EL3.NS == '0')
//            X<t,0x40> = ICC_AP1R_EL1_S<m>;
//        else
//            X<t,0x40> = ICC_AP1R_EL1_NS<m>;

// AMEVCNTR0<m>_EL0
// encoding=OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '010', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_AMUv1))
//        Undefined()
//    else if (m >= 4)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (AArch64.AMUSERENR_EL0.EN == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HAFGRTR_EL2.AMEVCNTR0<m>_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = AMEVCNTR0_EL0<m>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HAFGRTR_EL2.AMEVCNTR0<m>_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = AMEVCNTR0_EL0<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = AMEVCNTR0_EL0<m>;
//    else if (PSTATE.EL == EL3)
//        X<t,0x40> = AMEVCNTR0_EL0<m>;

// AMEVTYPER0<m>_EL0
// encoding=OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '011', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_AMUv1))
//        Undefined()
//    else if (m >= 4)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (AArch64.AMUSERENR_EL0.EN == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = AMEVTYPER0_EL0<m>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = AMEVTYPER0_EL0<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = AMEVTYPER0_EL0<m>;
//    else if (PSTATE.EL == EL3)
//        X<t,0x40> = AMEVTYPER0_EL0<m>;

// AMEVCNTR1<m>_EL0
// encoding=OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '110', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_AMUv1))
//        Undefined()
//    else if (m >= NUM_AMU_CG1_MONITORS)
//        Undefined()
//    else if (!IsG1ActivityMonitorImplemented(m))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (AArch64.AMUSERENR_EL0.EN == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HAFGRTR_EL2.AMEVCNTR1<m>_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.AMCR_EL0.CG1RZ == '1')
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = AMEVCNTR1_EL0<m>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HAFGRTR_EL2.AMEVCNTR1<m>_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsHighestEL(PSTATE.EL) && AArch64.AMCR_EL0.CG1RZ == '1')
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = AMEVCNTR1_EL0<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsHighestEL(PSTATE.EL) && AArch64.AMCR_EL0.CG1RZ == '1')
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = AMEVCNTR1_EL0<m>;
//    else if (PSTATE.EL == EL3)
//        X<t,0x40> = AMEVCNTR1_EL0<m>;

// AMEVTYPER1<m>_EL0
// encoding=OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '111', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_AMUv1))
//        Undefined()
//    else if (m >= NUM_AMU_CG1_MONITORS)
//        Undefined()
//    else if (!IsG1ActivityMonitorImplemented(m))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (AArch64.AMUSERENR_EL0.EN == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HAFGRTR_EL2.AMEVTYPER1<m>_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = AMEVTYPER1_EL0<m>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HAFGRTR_EL2.AMEVTYPER1<m>_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = AMEVTYPER1_EL0<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = AMEVTYPER1_EL0<m>;
//    else if (PSTATE.EL == EL3)
//        X<t,0x40> = AMEVTYPER1_EL0<m>;

// PMEVCNTR<m>_EL0
// encoding=OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '10', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_PMUv3))
//        Undefined()
//    else if (m >= GetNumEventCountersSelfHosted())
//        if (IsFeatureImplemented(FEAT_FGT))
//            Undefined()
//        else
//            ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (   (   IsFeatureImplemented(FEAT_PMUv3p9)
         //            && (AArch64.PMUSERENR_EL0.UEN):(AArch64.PMUSERENR_EL0.ER):(AArch64.PMUSERENR_EL0.EN) == '000')
         //        || (!IsFeatureImplemented(FEAT_PMUv3p9) && (AArch64.PMUSERENR_EL0.ER):(AArch64.PMUSERENR_EL0.EN) == '00'))
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.PMEVCNTRn_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && m >= GetNumEventCountersAccessible())
//            if (!IsFeatureImplemented(FEAT_FGT))
//                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//            else
//                AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1' && (AArch64.PMUACR_EL1)<m> == '0')
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = PMEVCNTR_EL0<m>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.PMEVCNTRn_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && m >= GetNumEventCountersAccessible())
//            if (!IsFeatureImplemented(FEAT_FGT))
//                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//            else
//                AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = PMEVCNTR_EL0<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = PMEVCNTR_EL0<m>;
//    else if (PSTATE.EL == EL3)
//        X<t,0x40> = PMEVCNTR_EL0<m>;

// PMEVTYPER<m>_EL0
// encoding=OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '11', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_PMUv3))
//        Undefined()
//    else if (m >= GetNumEventCountersSelfHosted())
//        if (IsFeatureImplemented(FEAT_FGT))
//            Undefined()
//        else
//            ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.PMEVTYPERn_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && m >= GetNumEventCountersAccessible())
//            if (!IsFeatureImplemented(FEAT_FGT))
//                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//            else
//                AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1' && (AArch64.PMUACR_EL1)<m> == '0')
//            X<t,0x40> = Zeros(0x40);
//        else
//            X<t,0x40> = PMEVTYPER_EL0<m>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGRTR_EL2.PMEVTYPERn_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && m >= GetNumEventCountersAccessible())
//            if (!IsFeatureImplemented(FEAT_FGT))
//                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//            else
//                AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = PMEVTYPER_EL0<m>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = PMEVTYPER_EL0<m>;
//    else if (PSTATE.EL == EL3)
//        X<t,0x40> = PMEVTYPER_EL0<m>;

// ICH_AP0R<m>_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1000', 'op2': '0'})
//    if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
//        Undefined()
//    else if (m == 1 && NUM_GIC_PREEMPTION_BITS < 6)
//        Undefined()
//    else if ((m == 2 || m == 3) && NUM_GIC_PREEMPTION_BITS < 7)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            X<t,0x40> = NVMem<0x480 + 8 * m>;
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (AArch64.ICC_SRE_EL2.SRE == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            X<t,0x40> = ICH_AP0R_EL2<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.ICC_SRE_EL3.SRE == '0')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = ICH_AP0R_EL2<m>;

// ICH_AP1R<m>_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1001', 'op2': '0'})
//    if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
//        Undefined()
//    else if (m == 1 && NUM_GIC_PREEMPTION_BITS < 6)
//        Undefined()
//    else if ((m == 2 || m == 3) && NUM_GIC_PREEMPTION_BITS < 7)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            X<t,0x40> = NVMem<0x4a0 + 8 * m>;
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (AArch64.ICC_SRE_EL2.SRE == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            X<t,0x40> = ICH_AP1R_EL2<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.ICC_SRE_EL3.SRE == '0')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = ICH_AP1R_EL2<m>;

// ICH_LR<m>_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '110', 'op2': (m)[0:2]})
//    if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
//        Undefined()
//    else if (m >= NUM_GIC_LIST_REGS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            X<t,0x40> = NVMem<0x400 + 8 * m>;
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (AArch64.ICC_SRE_EL2.SRE == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            X<t,0x40> = ICH_LR_EL2<m>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.ICC_SRE_EL3.SRE == '0')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = ICH_LR_EL2<m>;

// AMEVCNTVOFF0<m>_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1101', 'CRm': '100', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_AMUv1p1))
//        Undefined()
//    else if (m >= 4)
//        Undefined()
//    else if (!(m IN (0, 2, 3)))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            X<t,0x40> = NVMem<0xa00 + 8 * m>;
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AMVOFFEN == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.AMVOFFEN == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = AMEVCNTVOFF0_EL2<m>;
//    else if (PSTATE.EL == EL3)
//        X<t,0x40> = AMEVCNTVOFF0_EL2<m>;

// AMEVCNTVOFF1<m>_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1101', 'CRm': '101', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_AMUv1p1))
//        Undefined()
//    else if (m >= NUM_AMU_CG1_MONITORS)
//        Undefined()
//    else if (!IsG1ActivityMonitorOffsetImplemented(m))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            X<t,0x40> = NVMem<0xa80 + 8 * m>;
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AMVOFFEN == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.AMVOFFEN == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            X<t,0x40> = AMEVCNTVOFF1_EL2<m>;
//    else if (PSTATE.EL == EL3)
//        X<t,0x40> = AMEVCNTVOFF1_EL2<m>;

// S3_<op1>_C<Cn>_C<Cm>_<op2>
// encoding=OrderedDict({'op0': '11', 'op1': op1[0:2], 'CRn': '1x11', 'CRm': Cm[0:3], 'op2': op2[0:2]})
//    if (PSTATE.EL == EL0)
//        if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.TIDCP == '1')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.TIDCP == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            AArch64_ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t)
//    else if (PSTATE.EL == EL1)
//        if (EL2Enabled() && AArch64.HCR_EL2.TIDCP == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            AArch64_ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t)
//    else if (PSTATE.EL == EL2)
//        AArch64_ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t)
//    else if (PSTATE.EL == EL3)
//        AArch64_ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t)

/**
 * Implements the A64.MRS instruction (generic).
 *
 * @returns Strict VBox status code.
 * @param   pVCpu       The cross context virtual CPU structure of the
 *                      calling thread.
 * @param   idSysReg    The system register to read (IPRT format).
 * @param   idxGprDst   The destination GPR register number (for exceptions).
 * @param   puDst       Where to return the value.
 */
DECLHIDDEN(VBOXSTRICTRC) iemCImplA64_mrs_generic(PVMCPU pVCpu, uint32_t idSysReg, uint32_t idxGprDst, uint64_t * puDst)
{
    Log(("iemCImplA64_mrs(%#x)\n", idSysReg));
    uint32_t const uInstrEssence = IEM_CIMPL_SYSREG_INSTR_ESSENCE_MAKE(idSysReg, idxGprDst, 0, 0xf);
    switch (idSysReg)
    {
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_OSDTRRX_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_OSDTRRX_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MDCCINT_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MDCCINT_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MDSCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MDSCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlags(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_OSDTRTX_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_OSDTRTX_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MDSELR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MDSELR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,5,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MDSTEPOP_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MDSTEPOP_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,6,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_OSECCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_OSECCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MDRAR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MDRAR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_OSLSR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_OSLSR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,3,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_OSDLR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_OSDLR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DBGPRCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_DBGPRCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,14,11,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMCCNTSVR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMCCNTSVR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,14,12,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMICNTSVR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMICNTSVR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,14,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DBGAUTHSTATUS_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_DBGAUTHSTATUS_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,8,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DBGCLAIMSET_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_DBGCLAIMSET_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,9,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DBGCLAIMCLR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_DBGCLAIMCLR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMACCESSR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMACCESSR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMIIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMIIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMDEVARCH_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMDEVARCH_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMDEVAFF_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMDEVAFF_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMCFGR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMCFGR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,14,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMINTENSET_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMINTENSET_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,14,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMINTENCLR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMINTENCLR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCTRACEIDR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCTRACEIDR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCVICTLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCVICTLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR8(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR8 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIMSPEC0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIMSPEC0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCPRGCTLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCPRGCTLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCQCTLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCQCTLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCVIIECTLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCVIIECTLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR9(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR9 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCRSR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCRSR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,11,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCSTALLCTLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCSTALLCTLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,11,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR3(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCTSCTLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCTSCTLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR4(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR4 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCSYNCPR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCSYNCPR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR5(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR5 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,14,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCCCCTLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCCCCTLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,14,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR6(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR6 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,15,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCBBCTLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCBBCTLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,15,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR7(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR7 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCITEEDCR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCITEEDCR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCVISSCTLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCVISSCTLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR10(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR10 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCSTATR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCSTATR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCVIPCSSCTLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCVIPCSSCTLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR11(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR11 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCCONFIGR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCCONFIGR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,4,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,5,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR13(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR13 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCAUXCTLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCAUXCTLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCSEQRSTEVR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCSEQRSTEVR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,7,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCSEQSTR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCSEQSTR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCEVENTCTL0R(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCEVENTCTL0R -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,9,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCEVENTCTL1R(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCEVENTCTL1R -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,9,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCIDR1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCIDR1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,1,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCOSLSR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCOSLSR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCCIDCCTLR0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCCIDCCTLR0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCCIDCCTLR1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCCIDCCTLR1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCVMIDCCTLR0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCVMIDCCTLR0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCVMIDCCTLR1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCVMIDCCTLR1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,14,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCAUTHSTATUS(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCAUTHSTATUS -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,15,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCDEVARCH(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCDEVARCH -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,2,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCDEVID(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCDEVID -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,8,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCCLAIMSET(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCCLAIMSET -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,9,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCCLAIMCLR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCCLAIMCLR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_BRBCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_BRBCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_BRBFCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_BRBFCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_BRBTS_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_BRBTS_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_BRBINFINJ_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_BRBINFINJ_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_BRBSRCINJ_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_BRBSRCINJ_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_BRBTGTINJ_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_BRBTGTINJ_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_BRBIDR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_BRBIDR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,0,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MDCCSR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MDCCSR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,0,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DBGDTR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_DBGDTR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,0,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DBGDTRRX_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_DBGDTRRX_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMCR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMCR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMCNTENSET_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMCNTENSET_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMCNTENCLR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMCNTENCLR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMOVSCLR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMOVSCLR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMSELR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMSELR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,14,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMOVSSET_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMOVSSET_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,0,7,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DBGVCR32_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_DBGVCR32_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_BRBCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_BRBCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,13,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMACCESSR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMACCESSR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,5,9,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_BRBCR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_BRBCR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,5,9,13,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMACCESSR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPMACCESSR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,6,9,13,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMACCESSR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SPMACCESSR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,6,9,14,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMROOTCR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SPMROOTCR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,7,9,14,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPMSCR_EL1(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SPMSCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_REVIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_REVIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_PFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_PFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_PFR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_PFR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_DFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_DFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_MMFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_MMFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_MMFR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_MMFR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_MMFR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_MMFR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,1,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_MMFR3_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_MMFR3_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_ISAR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_ISAR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_ISAR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_ISAR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_ISAR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_ISAR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_ISAR3_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_ISAR3_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_ISAR4_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_ISAR4_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_ISAR5_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_ISAR5_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_MMFR4_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_MMFR4_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,2,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_ISAR6_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_ISAR6_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MVFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MVFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MVFR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MVFR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MVFR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MVFR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_PFR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_PFR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_DFR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_DFR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,3,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_MMFR5_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_MMFR5_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64PFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64PFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64PFR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64PFR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64PFR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64PFR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64ZFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64ZFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64SMFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64SMFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,4,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64FPFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64FPFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64DFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64DFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64DFR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64DFR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64DFR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64DFR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64AFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64AFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64AFR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64AFR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64ISAR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64ISAR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64ISAR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64ISAR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64ISAR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64ISAR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,6,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64ISAR3_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64ISAR3_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64MMFR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64MMFR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64MMFR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64MMFR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64MMFR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64MMFR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64MMFR3_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64MMFR3_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,0,7,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ID_AA64MMFR4_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ID_AA64MMFR4_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ACTLR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ACTLR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CPACR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CPACR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_RGSR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_RGSR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_GCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ZCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ZCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRFCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRFCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCITECR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCITECR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SMPRI_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SMPRI_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SMCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SMCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLRMASK_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLRMASK_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ACTLRMASK_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ACTLRMASK_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CPACRMASK_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CPACRMASK_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR2MASK_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLR2MASK_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CPACRALIAS_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CPACRALIAS_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ACTLRALIAS_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ACTLRALIAS_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLRALIAS_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLRALIAS_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR2ALIAS_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLR2ALIAS_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MAIR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MAIR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MAIR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MAIR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PIRE0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PIRE0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PIR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PIR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_POR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_POR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_S2POR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_S2POR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMAIR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMAIR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMAIR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMAIR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_LORSA_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_LORSA_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_LOREA_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_LOREA_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_LORN_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_LORN_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_LORC_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_LORC_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMBWIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMBWIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_LORID_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_LORID_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAM1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAM1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAM0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAM0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMSM_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMSM_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMBW1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMBW1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMBW0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMBW0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMBWSM_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMBWSM_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VBAR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_VBAR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_RVBAR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_RVBAR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_RMR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_RMR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ISR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ISR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DISR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_DISR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_RPR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_RPR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_IAR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_IAR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_HPPIR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_HPPIR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_BPR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_BPR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_CTLR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_CTLR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_SRE_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_SRE_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_IGRPEN0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_IGRPEN0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_IGRPEN1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_IGRPEN1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_IAR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_IAR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_HPPIR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_HPPIR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_BPR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_BPR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,9,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_NMIAR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_NMIAR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CONTEXTIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CONTEXTIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_RCWSMASK_EL1(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_RCWSMASK_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TPIDR_EL1(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_TPIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ACCDATA_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ACCDATA_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_RCWMASK_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_RCWMASK_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCXTNUM_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCXTNUM_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,14,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTKCTL_EL1(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CNTKCTL_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TTBR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TTBR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TTBR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TTBR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_APIAKeyLo_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_APIAKeyLo_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_APIAKeyHi_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_APIAKeyHi_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_APIBKeyLo_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_APIBKeyLo_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,1,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_APIBKeyHi_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_APIBKeyHi_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_APDAKeyLo_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_APDAKeyLo_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_APDAKeyHi_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_APDAKeyHi_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_APDBKeyLo_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_APDBKeyLo_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_APDBKeyHi_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_APDBKeyHi_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_APGAKeyLo_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_APGAKeyLo_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_APGAKeyHi_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_APGAKeyHi_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GCSCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_GCSCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GCSPR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_GCSPR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GCSCRE0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_GCSCRE0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCRMASK_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCRMASK_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCR2MASK_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCR2MASK_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCRALIAS_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCRALIAS_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCR2ALIAS_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCR2ALIAS_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPSR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPSR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ELR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ELR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SP_EL0(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SP_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPSel(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SPSel -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CurrentEL(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CurrentEL -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PAN(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_PAN -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_UAO(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_UAO -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ALLINT(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_ALLINT -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PM(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_PM -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_PMR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_PMR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AFSR0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AFSR0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AFSR1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AFSR1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ESR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ESR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERRIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERRIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERRSELR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERRSELR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXGSR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXGSR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXFR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXFR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXCTLR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXCTLR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXSTATUS_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXSTATUS_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXADDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXADDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXPFGF_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXPFGF_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXPFGCTL_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXPFGCTL_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXPFGCDN_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXPFGCDN_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXMISC0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXMISC0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXMISC1_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXMISC1_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXMISC2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXMISC2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ERXMISC3_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ERXMISC3_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TFSR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TFSR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TFSRE0_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TFSRE0_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,6,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_FAR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_FAR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,6,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PFAR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PFAR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,7,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PAR_EL1(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_PAR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMBLIMITR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMBLIMITR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMBPTR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMBPTR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMBSR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMBSR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSDSFR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSDSFR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMBMAR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMBMAR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMBIDR_EL1(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_PMBIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRBLIMITR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRBLIMITR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRBPTR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRBPTR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRBBASER_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRBBASER_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRBSR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRBSR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRBMAR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRBMAR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRBMPAM_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRBMPAM_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRBTRG_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRBTRG_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRBIDR_EL1(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_TRBIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,13,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSSCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSSCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMINTENSET_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMINTENSET_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMINTENCLR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMINTENCLR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMUACR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMUACR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMECR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMECR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMMIR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMMIR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMIAR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMIAR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSNEVFR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSNEVFR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSICR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSICR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSIRR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSIRR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSFCR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSFCR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSEVFR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSEVFR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSLATFR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSLATFR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CCSIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CCSIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CLIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CLIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CCSIDR2_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CCSIDR2_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GMID_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_GMID_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SMIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SMIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,1,0,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AIDR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AIDR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,2,0,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CSSELR_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CSSELR_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,0,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CTR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CTR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,0,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DCZID_EL0(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_DCZID_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,10,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_POR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_POR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TPIDR_EL0(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_TPIDR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TPIDRRO_EL0(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_TPIDRRO_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TPIDR2_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TPIDR2_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCXTNUM_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCXTNUM_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMCR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMCR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMCFGR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMCFGR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMCGCR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMCGCR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMUSERENR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMUSERENR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMCNTENCLR0_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMCNTENCLR0_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMCNTENSET0_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMCNTENSET0_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMCG1IDR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMCG1IDR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMCNTENCLR1_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMCNTENCLR1_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMCNTENSET1_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMCNTENSET1_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTFRQ_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTFRQ_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTPCT_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTPCT_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTVCT_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTVCT_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTPCTSS_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTPCTSS_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTVCTSS_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTVCTSS_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMCCFILTR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMCCFILTR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTP_TVAL_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTP_TVAL_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTP_CTL_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTP_CTL_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTP_CVAL_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTP_CVAL_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTV_TVAL_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTV_TVAL_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTV_CTL_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTV_CTL_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTV_CVAL_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTV_CVAL_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,2,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_RNDR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_RNDR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,2,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_RNDRRS(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_RNDRRS -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,2,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GCSPR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_GCSPR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_NZCV(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_NZCV -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DAIF(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_DAIF -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SVCR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SVCR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DIT(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_DIT -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SSBS(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SSBS -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCO(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_TCO -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_FPCR(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_FPCR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_FPSR(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_FPSR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_FPMR(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_FPMR -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DSPSR_EL0(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_DSPSR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DLR_EL0(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_DLR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMCR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMCR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMCNTENSET_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMCNTENSET_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMCNTENCLR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMCNTENCLR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMOVSCLR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMOVSCLR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSELR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSELR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMCEID0_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMCEID0_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMCEID1_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMCEID1_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMCCNTR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMCCNTR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMXEVTYPER_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMXEVTYPER_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMXEVCNTR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMXEVCNTR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMUSERENR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMUSERENR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMOVSSET_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMOVSSET_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMICNTR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMICNTR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMICFILTR_EL0(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMICFILTR_EL0 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,0,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VPIDR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_VPIDR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,0,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VMPIDR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_VMPIDR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlagsAndPgmModeEl2(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ACTLR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ACTLR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR2_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLR2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlags(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MDCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MDCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CPTR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CPTR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HSTR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HSTR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HFGRTR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HFGRTR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HFGWTR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HFGWTR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HFGITR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HFGITR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HACR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HACR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ZCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ZCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRFCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRFCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HCRX_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HCRX_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlags(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCITECR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCITECR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SMPRIMAP_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SMPRIMAP_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SMCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SMCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SDER32_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SDER32_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLRMASK_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLRMASK_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ACTLRMASK_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ACTLRMASK_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CPTRMASK_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CPTRMASK_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR2MASK_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLR2MASK_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MAIR2_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MAIR2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MAIR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MAIR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PIRE0_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PIRE0_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PIR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PIR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_POR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_POR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_S2PIR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_S2PIR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMAIR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMAIR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMAIR2_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMAIR2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMHCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMHCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMVPMV_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMVPMV_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAM2_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAM2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMBW2_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMBW2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMBWCAP_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMBWCAP_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMVPM0_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMVPM0_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMVPM1_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMVPM1_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMVPM2_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMVPM2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMVPM3_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMVPM3_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMVPM4_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMVPM4_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMVPM5_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMVPM5_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMVPM6_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMVPM6_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMVPM7_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMVPM7_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,8,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MECID_P0_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MECID_P0_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,8,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MECID_A0_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MECID_A0_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,8,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MECID_P1_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MECID_P1_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,8,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MECID_A1_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MECID_A1_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,8,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MECIDR_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MECIDR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,9,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VMECID_P_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_VMECID_P_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,9,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VMECID_A_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_VMECID_A_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VBAR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_VBAR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_RVBAR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_RVBAR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_RMR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_RMR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VDISR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_VDISR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICH_HCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICH_HCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICH_VTR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICH_VTR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICH_MISR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICH_MISR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICH_EISR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICH_EISR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICH_ELRSR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICH_ELRSR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICH_VMCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICH_VMCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,9,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_SRE_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ICC_SRE_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CONTEXTIDR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CONTEXTIDR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TPIDR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TPIDR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCXTNUM_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCXTNUM_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTVOFF_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTVOFF_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTPOFF_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTPOFF_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHCTL_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTHCTL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHP_TVAL_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTHP_TVAL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHP_CTL_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTHP_CTL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHP_CVAL_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTHP_CVAL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHV_TVAL_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTHV_TVAL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHV_CTL_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTHV_CTL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHV_CVAL_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTHV_CVAL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHVS_TVAL_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CNTHVS_TVAL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHVS_CTL_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CNTHVS_CTL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHVS_CVAL_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CNTHVS_CVAL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHPS_TVAL_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CNTHPS_TVAL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHPS_CTL_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CNTHPS_CTL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,5,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTHPS_CVAL_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CNTHPS_CVAL_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TTBR0_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TTBR0_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TTBR1_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TTBR1_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlagsAndPgmModeEl2(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCR2_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCR2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VTTBR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_VTTBR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VTCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_VTCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VNCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_VNCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HDBSSBR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HDBSSBR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HDBSSPROD_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HDBSSPROD_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HACDBSBR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HACDBSBR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HACDBSCONS_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HACDBSCONS_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GCSCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_GCSCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GCSPR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_GCSPR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VSTTBR_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_VSTTBR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,6,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VSTCR_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_VSTCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCRMASK_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCRMASK_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCR2MASK_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCR2MASK_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_DACR32_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_DACR32_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HDFGRTR2_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_HDFGRTR2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HDFGWTR2_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_HDFGWTR2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HFGRTR2_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_HFGRTR2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HFGWTR2_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_HFGWTR2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HDFGRTR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HDFGRTR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HDFGWTR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HDFGWTR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HAFGRTR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HAFGRTR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HFGITR2_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_HFGITR2_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPSR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPSR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ELR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ELR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SP_EL1(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SP_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPSR_irq(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPSR_irq -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPSR_abt(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPSR_abt -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPSR_und(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPSR_und -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPSR_fiq(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPSR_fiq -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_IFSR32_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_IFSR32_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AFSR0_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AFSR0_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AFSR1_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AFSR1_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ESR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ESR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VSESR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_VSESR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_FPEXC32_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_FPEXC32_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TFSR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TFSR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,6,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_FAR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_FAR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,6,0,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_HPFAR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_HPFAR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,6,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PFAR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PFAR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,10,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMBSR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMBSR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,11,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRBSR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRBSR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,9,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSCR_EL2(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSCR_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ACTLR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ACTLR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CPACR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CPACR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR2_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLR2_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ZCR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ZCR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRFCR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRFCR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRCITECR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRCITECR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SMCR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SMCR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLRMASK_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLRMASK_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ACTLRMASK_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ACTLRMASK_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CPACRMASK_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CPACRMASK_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR2MASK_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCTLR2MASK_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MAIR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MAIR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MAIR2_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MAIR2_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PIRE0_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PIRE0_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PIR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PIR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_POR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_POR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMAIR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMAIR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMAIR2_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AMAIR2_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAM1_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAM1_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,5,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMBW1_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_MPAMBW1_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,12,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VBAR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_VBAR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,13,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CONTEXTIDR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CONTEXTIDR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,13,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCXTNUM_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SCXTNUM_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTKCTL_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTKCTL_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTP_TVAL_EL02(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTP_TVAL_EL02 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTP_CTL_EL02(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTP_CTL_EL02 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTP_CVAL_EL02(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTP_CVAL_EL02 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTV_TVAL_EL02(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTV_TVAL_EL02 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTV_CTL_EL02(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTV_CTL_EL02 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTV_CVAL_EL02(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_CNTV_CVAL_EL02 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TTBR0_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TTBR0_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TTBR1_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TTBR1_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCR2_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCR2_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GCSCR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_GCSCR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GCSPR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_GCSPR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,7,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCRMASK_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCRMASK_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCR2MASK_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TCR2MASK_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,4,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPSR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_SPSR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,4,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ELR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ELR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,5,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AFSR0_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AFSR0_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,5,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AFSR1_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_AFSR1_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,5,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ESR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_ESR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,5,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TFSR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TFSR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,6,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_FAR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_FAR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,6,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PFAR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PFAR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,9,10,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMBSR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMBSR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,9,11,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRBSR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_TRBSR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,9,9,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMSCR_EL12(pVCpu, puDst, uInstrEssence);
            LogFlow(("iemCImplA64_mrs_PMSCR_EL12 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SCTLR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlagsAndPgmModeEl3(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ACTLR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_ACTLR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCTLR2_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SCTLR2_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SCR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlags(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SDER32_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SDER32_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CPTR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CPTR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_FGWTE3_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_FGWTE3_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ZCR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_ZCR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SMCR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SMCR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MDCR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MDCR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MAIR2_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MAIR2_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,10,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MECID_RL_A_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MECID_RL_A_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MAIR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MAIR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PIR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_PIR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_POR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_POR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMAIR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_AMAIR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AMAIR2_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_AMAIR2_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAM3_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MPAM3_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,5,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MPAMBW3_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MPAMBW3_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VBAR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_VBAR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_RVBAR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_RVBAR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_RMR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_RMR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VDISR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_VDISR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,12,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_CTLR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_ICC_CTLR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,12,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_SRE_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_ICC_SRE_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,12,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ICC_IGRPEN1_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_ICC_IGRPEN1_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,13,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TPIDR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_TPIDR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,13,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SCXTNUM_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SCXTNUM_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TTBR0_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_TTBR0_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TCR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_TCR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return iemCImplHlpRecalcFlagsAndPgmModeEl3(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GPTBR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_GPTBR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GPCBW_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_GPCBW_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,1,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GPCCR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_GPCCR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GCSCR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_GCSCR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_GCSPR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_GCSPR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,4,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SPSR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SPSR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,4,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ELR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_ELR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,4,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_SP_EL2(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_SP_EL2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,5,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AFSR0_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_AFSR0_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,5,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_AFSR1_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_AFSR1_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,5,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_ESR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_ESR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,5,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_VSESR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_VSESR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,5,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TFSR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_TFSR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,6,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_FAR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_FAR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,6,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_MFAR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_MFAR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,9,10,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_PMBSR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_PMBSR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,9,11,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_TRBSR_EL3(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_TRBSR_EL3 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,7,14,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTPS_TVAL_EL1(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CNTPS_TVAL_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,7,14,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTPS_CTL_EL1(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CNTPS_CTL_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,7,14,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_mrs_CNTPS_CVAL_EL1(pVCpu, puDst);
            LogFlow(("iemCImplA64_mrs_CNTPS_CVAL_EL1 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
    }
    /* Fall back on handcoded handler. */
    return iemCImplA64_mrs_fallback(pVCpu, idSysReg, idxGprDst, puDst);
}

/**
 * Implements the A64.MRS instruction.
 *
 * @param   idSysReg    The system register to read (IPRT format).
 * @param   idxGprDst   The destination GPR register number (for exceptions).
 */
IEM_CIMPL_DEF_2(iemCImplA64_mrs, uint32_t, idSysReg, uint32_t, idxGprDst)
{
    uint64_t         uZeroDummy;
    uint64_t * const puDst = idxGprDst < ARMV8_A64_REG_XZR
                           ? &pVCpu->cpum.GstCtx.aGRegs[idxGprDst].x : &uZeroDummy;
    return iemCImplA64_mrs_generic(pVCpu, idSysReg, idxGprDst, puDst);
}



/*
 * A64.MSRregister
 *
 *  498 registers
 *  393 complete - 283 with unresolved registers
 *   70 incomplete
 *
 * Warnings:
 *   Assignment to Identifier: Unable to map AArch64.ICV_BPR0_EL1 to anything
 *   Assignment to Identifier: Unable to map AArch64.ICV_BPR1_EL1 to anything
 *   Assignment to Identifier: Unable to map AArch64.ICV_CTLR_EL1 to anything (2 times)
 *   Assignment to Identifier: Unable to map AArch64.ICV_DIR_EL1 to anything (2 times)
 *   Assignment to Identifier: Unable to map AArch64.ICV_EOIR0_EL1 to anything
 *   Assignment to Identifier: Unable to map AArch64.ICV_EOIR1_EL1 to anything
 *   Assignment to Identifier: Unable to map AArch64.ICV_IGRPEN0_EL1 to anything
 *   Assignment to Identifier: Unable to map AArch64.ICV_IGRPEN1_EL1 to anything
 *   Assignment to Identifier: Unable to map AArch64.ICV_PMR_EL1 to anything (2 times)
 *   Assignment/Identifier: No CPUMCTX mapping for register AArch64.ACTLR_EL2
 *   Assignment/Identifier: No CPUMCTX mapping for register AArch64.RCWMASK_EL1 (2 times)
 *   Assignment/Identifier: No CPUMCTX mapping for register AArch64.RCWSMASK_EL1
 *   Assignment/Identifier: No CPUMCTX mapping for register AArch64.SCTLR2_EL1 (2 times)
 *   Assignment/Identifier: No CPUMCTX mapping for register AArch64.SCTLR2_EL2 (3 times)
 *   Assignment/Identifier: No CPUMCTX mapping for register AArch64.TCR2_EL1 (2 times)
 *   Assignment/Identifier: No CPUMCTX mapping for register AArch64.TCR2_EL2 (3 times)
 *   Call to untranslated function: CNTHCTL_EL2_VHE
 *   Call to untranslated function: ConstrainUnpredictableProcedure (6 times)
 *   Call to untranslated function: EffectiveACTLRMASK_EL2 (3 times)
 *   Call to untranslated function: EffectivePMSCR_EL2_EE
 *   Call to untranslated function: EffectiveSCTLR2MASK_EL1 (5 times)
 *   Call to untranslated function: EffectiveSCTLR2MASK_EL2 (8 times)
 *   Call to untranslated function: EffectiveTCR2MASK_EL1 (5 times)
 *   Call to untranslated function: EffectiveTCR2MASK_EL2 (8 times)
 *   Call to untranslated function: EffectiveTCRMASK_EL1 (5 times)
 *   Call to untranslated function: EffectiveTCRMASK_EL2 (8 times)
 *   Call to untranslated function: EffectiveTRFCR_EL2_EE (2 times)
 *   Call to untranslated function: GetNumEventCountersAccessible (4 times)
 *   Call to untranslated function: GetNumEventCountersSelfHosted (2 times)
 *   Call to untranslated function: UInt (91 times)
 *   Call to untranslated function: Write_DBGDTR_EL0 (6 times)
 *   Call to untranslated function: ZeroPMUCounters (3 times)
 *   Generic field: Field "F0" not found in register "PMUACR_EL1" (2 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICC_SRE_EL1 (looking up field SRE) (12 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICC_SRE_EL2 (looking up field Enable)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICC_SRE_EL2 (looking up field SRE) (14 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICH_HCR_EL2 (looking up field TALL0) (3 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICH_HCR_EL2 (looking up field TALL1) (3 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICH_HCR_EL2 (looking up field TC) (6 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.ICH_HCR_EL2 (looking up field TDIR)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAM2_EL2 (looking up field EnMPAMSM)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAM2_EL2 (looking up field TRAPMPAM0EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAM2_EL2 (looking up field TRAPMPAM1EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMBW2_EL2 (looking up field nTRAP_MPAMBW0_EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMBW2_EL2 (looking up field nTRAP_MPAMBW1_EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMBW2_EL2 (looking up field nTRAP_MPAMBWSM_EL1)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMIDR_EL1 (looking up field HAS_HCR) (11 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.MPAMIDR_EL1 (looking up field VPMR_MAX) (7 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.PMSELR_EL0 (looking up field SEL) (22 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.SPMSELR_EL0 (looking up field SYSPMUSEL) (62 times)
 *   Generic field: No CPUMCTX mapping for register AArch64.TRFCR_EL1 (looking up field EE)
 */


/**
 * OSDTRRX_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_OSDTRRX_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,0,2), "OSDTRRX_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,0,2), "OSDTRRX_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG))
    //     OSDTRRX_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         OSDTRRX_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         OSDTRRX_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     OSDTRRX_EL1 = X<t,0x40>;
}


/**
 * MDCCINT_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MDCCINT_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.MDccInt.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.MDccInt.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG))
    //     MDCCINT_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MDCCINT_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MDCCINT_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MDCCINT_EL1 = X<t,0x40>;
}


/**
 * MDSCR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MDSCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x158, uValue);
        pVCpu->cpum.GstCtx.Mdscr.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Mdscr.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.MDSCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x158> = X<t,0x40>;
    //     else
    //         MDSCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MDSCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MDSCR_EL1 = X<t,0x40>;
}


/**
 * OSDTRTX_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_OSDTRTX_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,3,2), "OSDTRTX_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,3,2), "OSDTRTX_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG))
    //     OSDTRTX_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         OSDTRTX_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         OSDTRTX_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     OSDTRTX_EL1 = X<t,0x40>;
}


/**
 * MDSELR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MDSELR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fDebugV8p9)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,4,2), "MDSELR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,4,2), "MDSELR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_Debugv8p9))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EBWE == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nMDSELR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EBWE == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MDSELR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EBWE == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EBWE == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MDSELR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MDSELR_EL1 = X<t,0x40>;
}


/**
 * MDSTEPOP_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0101', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MDSTEPOP_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fStep2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,5,2),
                                     "MDSTEPOP_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,5,2), "MDSTEPOP_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_STEP2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnSTEPOP == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nMDSTEPOP_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnSTEPOP == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MDSTEPOP_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnSTEPOP == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnSTEPOP == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MDSTEPOP_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MDSTEPOP_EL1 = X<t,0x40>;
}


/**
 * OSECCR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': '0110', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_OSECCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (!(pVCpu->cpum.GstCtx.fOsLck & UINT32_C(1)/*OSLK*/))
            return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,6,2), "OSECCR_EL1", uValue, uInstrEssence);
    }
    if (!(pVCpu->cpum.GstCtx.fOsLck & UINT32_C(1)/*OSLK*/))
        return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,6,2), "OSECCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.OSECCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.OSLSR_EL1.OSLK == '0')
    //         return;
    //     else
    //         OSECCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.OSLSR_EL1.OSLK == '0')
    //         return;
    //     else
    //         OSECCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.OSLSR_EL1.OSLK == '0')
    //         return;
    //     OSECCR_EL1 = X<t,0x40>;
}


/**
 * OSLAR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_OSLAR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x500) /*TDE,TDOSA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,0,4), "OSLAR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,0,4), "OSLAR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDOSA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.OSLAR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDOSA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDOSA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         OSLAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDOSA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDOSA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         OSLAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     OSLAR_EL1 = X<t,0x40>;
}


/**
 * OSDLR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0001', 'CRm': '0011', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_OSDLR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x500) /*TDE,TDOSA*/) && pGstFeats->fDoubleLock)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,3,4), "OSDLR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,3,4), "OSDLR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && AArch64.MDCR_EL3.TDOSA == '1'
    //         && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_DoubleLock)
    //              && AArch64.HDFGWTR_EL2.OSDLR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDOSA) != '00'
    //              && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL2.TDOSA")))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && AArch64.MDCR_EL3.TDOSA == '1'
    //              && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         OSDLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && AArch64.MDCR_EL3.TDOSA == '1'
    //         && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && AArch64.MDCR_EL3.TDOSA == '1'
    //              && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         OSDLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     OSDLR_EL1 = X<t,0x40>;
}


/**
 * DBGPRCR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_DBGPRCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x500) /*TDE,TDOSA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,4,4), "DBGPRCR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,4,4), "DBGPRCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDOSA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.DBGPRCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDOSA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDOSA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         DBGPRCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDOSA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDOSA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         DBGPRCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     DBGPRCR_EL1 = X<t,0x40>;
}


/**
 * DBGCLAIMSET_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0111', 'CRm': '1000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_DBGCLAIMSET_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,8,6),
                                     "DBGCLAIMSET_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,8,6), "DBGCLAIMSET_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.DBGCLAIM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         DBGCLAIMSET_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         DBGCLAIMSET_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     DBGCLAIMSET_EL1 = X<t,0x40>;
}


/**
 * DBGCLAIMCLR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0111', 'CRm': '1001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_DBGCLAIMCLR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,9,6),
                                     "DBGCLAIMCLR_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,9,6), "DBGCLAIMCLR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.DBGCLAIM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         DBGCLAIMCLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         DBGCLAIMCLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     DBGCLAIMCLR_EL1 = X<t,0x40>;
}


/**
 * SPMACCESSR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1001', 'CRm': '1101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMACCESSR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x8e8, uValue);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,3),
                                     "SPMACCESSR_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,13,3),
                                     "SPMACCESSR_EL2",
                                     uValue,
                                     uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,3), "SPMACCESSR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMACCESSR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x8e8> = X<t,0x40>;
    //     else
    //         SPMACCESSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         SPMACCESSR_EL2 = X<t,0x40>;
    //     else
    //         SPMACCESSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMACCESSR_EL1 = X<t,0x40>;
}


/**
 * SPMINTENSET_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '001'})
 * Transformation status: 15 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMINTENSET_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMINTENSET_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else
        SPMINTENSET_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMINTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMINTENSET_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMINTENSET_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMINTENSET_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
}


/**
 * SPMINTENCLR_EL1 - OrderedDict({'op0': '10', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '010'})
 * Transformation status: 15 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMINTENCLR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMINTENCLR_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else
        SPMINTENCLR_EL1<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMINTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMINTENCLR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMINTENCLR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMINTENCLR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
}


/**
 * TRCTRACEIDR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCTRACEIDR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,1), "TRCTRACEIDR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,1), "TRCTRACEIDR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCTRACEIDR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCTRACEIDR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCTRACEIDR = X<t,0x40>;
}


/**
 * TRCVICTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCVICTLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,2), "TRCVICTLR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,2), "TRCVICTLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRCVICTLR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVICTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVICTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVICTLR = X<t,0x40>;
}


/**
 * TRCIMSPEC0 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCIMSPEC0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,7), "TRCIMSPEC0", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,7), "TRCIMSPEC0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRCIMSPECn == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCIMSPEC0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCIMSPEC0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCIMSPEC0 = X<t,0x40>;
}


/**
 * TRCPRGCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCPRGCTLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,0), "TRCPRGCTLR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,0), "TRCPRGCTLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRCPRGCTLR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCPRGCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCPRGCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCPRGCTLR = X<t,0x40>;
}


/**
 * TRCQCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCQCTLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,7)) >> 14) & UINT32_C(1)/*QFILT*/) != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,1), "TRCQCTLR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,1), "TRCQCTLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR0.QFILT == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCQCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCQCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCQCTLR = X<t,0x40>;
}


/**
 * TRCVIIECTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCVIIECTLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || (iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) & UINT32_C(0xf)/*NUMACPAIRS*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,2), "TRCVIIECTLR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,2), "TRCVIIECTLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && UInt(AArch64.TRCIDR4.NUMACPAIRS) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVIIECTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVIIECTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVIIECTLR = X<t,0x40>;
}


/**
 * TRCRSR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCRSR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,0), "TRCRSR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,0), "TRCRSR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCRSR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCRSR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCRSR = X<t,0x40>;
}


/**
 * TRCSTALLCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCSTALLCTLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,11,7)) >> 26) & UINT32_C(1)/*STALLCTL*/) != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,11,0),
                                     "TRCSTALLCTLR",
                                     uValue,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,11,0), "TRCSTALLCTLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR3.STALLCTL == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSTALLCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSTALLCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSTALLCTLR = X<t,0x40>;
}


/**
 * TRCTSCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCTSCTLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || !(iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,7)) & UINT32_C(0x1f000000)/*TSSIZE*/))
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,0), "TRCTSCTLR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,0), "TRCTSCTLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR0.TSSIZE != '00000'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCTSCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCTSCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCTSCTLR = X<t,0x40>;
}


/**
 * TRCSYNCPR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCSYNCPR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,0), "TRCSYNCPR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,0), "TRCSYNCPR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSYNCPR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSYNCPR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSYNCPR = X<t,0x40>;
}


/**
 * TRCCCCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCCCCTLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,7)) >>  7) & UINT32_C(1)/*TRCCCI*/) != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,14,0), "TRCCCCTLR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,14,0), "TRCCCCTLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR0.TRCCCI == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCCCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCCCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCCCTLR = X<t,0x40>;
}


/**
 * TRCBBCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCBBCTLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,7)) >>  5) & UINT32_C(1)/*TRCBB*/) != 1
        || (iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) & UINT32_C(0xf)/*NUMACPAIRS*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,15,0), "TRCBBCTLR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,15,0), "TRCBBCTLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(   IsFeatureImplemented(FEAT_ETE)
    //     && IsFeatureImplemented(FEAT_TRC_SR)
    //     && AArch64.TRCIDR0.TRCBB == '1'
    //     && UInt(AArch64.TRCIDR4.NUMACPAIRS) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCBBCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCBBCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCBBCTLR = X<t,0x40>;
}


/**
 * TRCITEEDCR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCITEEDCR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr || !pGstFeats->fIte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,1), "TRCITEEDCR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,1), "TRCITEEDCR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && IsFeatureImplemented(FEAT_ITE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCITEEDCR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCITEEDCR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCITEEDCR = X<t,0x40>;
}


/**
 * TRCVISSCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCVISSCTLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || (iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) & UINT32_C(0xf)/*NUMACPAIRS*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,2), "TRCVISSCTLR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,2), "TRCVISSCTLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && UInt(AArch64.TRCIDR4.NUMACPAIRS) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVISSCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVISSCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVISSCTLR = X<t,0x40>;
}


/**
 * TRCVIPCSSCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCVIPCSSCTLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) >> 12) & UINT32_C(0xf)/*NUMPC*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,2),
                                     "TRCVIPCSSCTLR",
                                     uValue,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,2), "TRCVIPCSSCTLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && UInt(AArch64.TRCIDR4.NUMPC) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVIPCSSCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVIPCSSCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVIPCSSCTLR = X<t,0x40>;
}


/**
 * TRCCONFIGR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCCONFIGR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,4,0), "TRCCONFIGR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,4,0), "TRCCONFIGR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCONFIGR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCONFIGR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCONFIGR = X<t,0x40>;
}


/**
 * TRCAUXCTLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCAUXCTLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,0), "TRCAUXCTLR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,0), "TRCAUXCTLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRCAUXCTLR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCAUXCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCAUXCTLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCAUXCTLR = X<t,0x40>;
}


/**
 * TRCSEQRSTEVR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0110', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCSEQRSTEVR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || !(iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,7)) & UINT32_C(0xe000000)/*NUMSEQSTATE*/))
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,4),
                                     "TRCSEQRSTEVR",
                                     uValue,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,4), "TRCSEQRSTEVR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR5.NUMSEQSTATE != '000'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSEQRSTEVR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSEQRSTEVR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSEQRSTEVR = X<t,0x40>;
}


/**
 * TRCSEQSTR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0111', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCSEQSTR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || !(iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,7)) & UINT32_C(0xe000000)/*NUMSEQSTATE*/))
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,7,4), "TRCSEQSTR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,7,4), "TRCSEQSTR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR5.NUMSEQSTATE != '000'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRCSEQSTR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSEQSTR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSEQSTR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCSEQSTR = X<t,0x40>;
}


/**
 * TRCEVENTCTL0R - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCEVENTCTL0R(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || !(iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) & UINT32_C(0xf0000)/*NUMRSPAIR*/))
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,0),
                                     "TRCEVENTCTL0R",
                                     uValue,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,0), "TRCEVENTCTL0R", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && AArch64.TRCIDR4.NUMRSPAIR != '0000'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCEVENTCTL0R = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCEVENTCTL0R = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCEVENTCTL0R = X<t,0x40>;
}


/**
 * TRCEVENTCTL1R - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '1001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCEVENTCTL1R(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,9,0),
                                     "TRCEVENTCTL1R",
                                     uValue,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,9,0), "TRCEVENTCTL1R", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCEVENTCTL1R = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCEVENTCTL1R = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCEVENTCTL1R = X<t,0x40>;
}


/**
 * TRCCIDCCTLR0 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCCIDCCTLR0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) >> 24) & UINT32_C(0xf)/*NUMCIDC*/) <= 0
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,7)) >>  5) & UINT32_C(0x1f)/*CIDSIZE*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,0,2),
                                     "TRCCIDCCTLR0",
                                     uValue,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,0,2), "TRCCIDCCTLR0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(   IsFeatureImplemented(FEAT_ETE)
    //     && IsFeatureImplemented(FEAT_TRC_SR)
    //     && UInt(AArch64.TRCIDR4.NUMCIDC) > 0
    //     && UInt(AArch64.TRCIDR2.CIDSIZE) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCIDCCTLR0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCIDCCTLR0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCIDCCTLR0 = X<t,0x40>;
}


/**
 * TRCCIDCCTLR1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCCIDCCTLR1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) >> 24) & UINT32_C(0xf)/*NUMCIDC*/) <= 4
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,7)) >>  5) & UINT32_C(0x1f)/*CIDSIZE*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,1,2),
                                     "TRCCIDCCTLR1",
                                     uValue,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,1,2), "TRCCIDCCTLR1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(   IsFeatureImplemented(FEAT_ETE)
    //     && IsFeatureImplemented(FEAT_TRC_SR)
    //     && UInt(AArch64.TRCIDR4.NUMCIDC) > 4
    //     && UInt(AArch64.TRCIDR2.CIDSIZE) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCIDCCTLR1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCIDCCTLR1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCIDCCTLR1 = X<t,0x40>;
}


/**
 * TRCVMIDCCTLR0 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCVMIDCCTLR0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) >> 28) & UINT32_C(0xf)/*NUMVMIDC*/) <= 0
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,7)) >> 10) & UINT32_C(0x1f)/*VMIDSIZE*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,2,2),
                                     "TRCVMIDCCTLR0",
                                     uValue,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,2,2), "TRCVMIDCCTLR0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(   IsFeatureImplemented(FEAT_ETE)
    //     && IsFeatureImplemented(FEAT_TRC_SR)
    //     && UInt(AArch64.TRCIDR4.NUMVMIDC) > 0
    //     && UInt(AArch64.TRCIDR2.VMIDSIZE) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVMIDCCTLR0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVMIDCCTLR0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVMIDCCTLR0 = X<t,0x40>;
}


/**
 * TRCVMIDCCTLR1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCVMIDCCTLR1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   !pGstFeats->fEte
        || !pGstFeats->fTrcSr
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,7)) >> 28) & UINT32_C(0xf)/*NUMVMIDC*/) <= 4
        || ((iemCImplHlpGetIdSysReg(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,7)) >> 10) & UINT32_C(0x1f)/*VMIDSIZE*/) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,3,2),
                                     "TRCVMIDCCTLR1",
                                     uValue,
                                     uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,3,2), "TRCVMIDCCTLR1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(   IsFeatureImplemented(FEAT_ETE)
    //     && IsFeatureImplemented(FEAT_TRC_SR)
    //     && UInt(AArch64.TRCIDR4.NUMVMIDC) > 4
    //     && UInt(AArch64.TRCIDR2.VMIDSIZE) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVMIDCCTLR1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVMIDCCTLR1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCVMIDCCTLR1 = X<t,0x40>;
}


/**
 * TRCCLAIMSET - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0111', 'CRm': '1000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCCLAIMSET(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,8,6), "TRCCLAIMSET", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,8,6), "TRCCLAIMSET", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRCCLAIM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCLAIMSET = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCLAIMSET = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCLAIMSET = X<t,0x40>;
}


/**
 * TRCCLAIMCLR - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0111', 'CRm': '1001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCCLAIMCLR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(28)/*TTA*/)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,9,6), "TRCCLAIMCLR", uValue, uInstrEssence);
    }
    if (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(20)/*TTA*/)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,9,6), "TRCCLAIMCLR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.TTA == '1')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRCCLAIM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCLAIMCLR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
    //         Undefined()
    //     else if (AArch64.CPTR_EL2.TTA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCLAIMCLR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TTA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRCCLAIMCLR = X<t,0x40>;
}


/**
 * BRBCR_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_BRBCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x8e0, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,0), "BRBCR_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,0,0), "BRBCR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,0), "BRBCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.nBRBCTL == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x8e0> = X<t,0x40>;
    //     else
    //         BRBCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         BRBCR_EL2 = X<t,0x40>;
    //     else
    //         BRBCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     BRBCR_EL1 = X<t,0x40>;
}


/**
 * BRBFCR_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_BRBFCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,1), "BRBFCR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,1), "BRBFCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.nBRBCTL == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRBFCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRBFCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     BRBFCR_EL1 = X<t,0x40>;
}


/**
 * BRBTS_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_BRBTS_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,2), "BRBTS_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,2), "BRBTS_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.nBRBDATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRBTS_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRBTS_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     BRBTS_EL1 = X<t,0x40>;
}


/**
 * BRBINFINJ_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_BRBINFINJ_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,0),
                                     "BRBINFINJ_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,0), "BRBINFINJ_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.nBRBDATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRBINFINJ_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRBINFINJ_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     BRBINFINJ_EL1 = X<t,0x40>;
}


/**
 * BRBSRCINJ_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_BRBSRCINJ_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,1),
                                     "BRBSRCINJ_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,1), "BRBSRCINJ_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.nBRBDATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRBSRCINJ_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRBSRCINJ_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     BRBSRCINJ_EL1 = X<t,0x40>;
}


/**
 * BRBTGTINJ_EL1 - OrderedDict({'op0': '10', 'op1': '001', 'CRn': '1001', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_BRBTGTINJ_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,2),
                                     "BRBTGTINJ_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,2), "BRBTGTINJ_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.nBRBDATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRBTGTINJ_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRBTGTINJ_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     BRBTGTINJ_EL1 = X<t,0x40>;
}


/**
 * DBGDTR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '0000', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 12 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_DBGDTR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_32(12)/*TDCC*/)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
                || (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/)))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        Write_DBGDTR_EL0(X<t,0x40>)
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        Write_DBGDTR_EL0(X<t,0x40>)
    }
    else
        Write_DBGDTR_EL0(X<t,0x40>)
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (Halted())
    //     Write_DBGDTR_EL0(X<t,0x40>)
    // else if (PSTATE.EL == EL0)
    //     if (AArch64.MDSCR_EL1.TDCC == '1')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.HCR_EL2.TGE == '1' || (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         Write_DBGDTR_EL0(X<t,0x40>)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         Write_DBGDTR_EL0(X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         Write_DBGDTR_EL0(X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     Write_DBGDTR_EL0(X<t,0x40>)
}


/**
 * DBGDTRTX_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '0000', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 12 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_DBGDTRTX_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_32(12)/*TDCC*/)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
                || (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/)))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        Write_DBGDTR_EL0(X<t,0x20>)
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(27)/*TDCC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & UINT64_C(0x300) /*TDE,TDA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        Write_DBGDTR_EL0(X<t,0x20>)
    }
    else
        Write_DBGDTR_EL0(X<t,0x20>)
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (Halted())
    //     Write_DBGDTR_EL0(X<t,0x20>)
    // else if (PSTATE.EL == EL0)
    //     if (AArch64.MDSCR_EL1.TDCC == '1')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.HCR_EL2.TGE == '1' || (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         Write_DBGDTR_EL0(X<t,0x20>)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL2.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         Write_DBGDTR_EL0(X<t,0x20>)
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && AArch64.MDCR_EL3.TDCC == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         Write_DBGDTR_EL0(X<t,0x20>)
    // else if (PSTATE.EL == EL3)
    //     Write_DBGDTR_EL0(X<t,0x20>)
}


/**
 * SPMCR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '000'})
 * Transformation status: 33 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMCR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMCR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMCR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else
        SPMCR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   !ELIsInHost(EL0)
    //              &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMCR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMCR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMCR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMCR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMCR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMCR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
}


/**
 * SPMCNTENSET_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '001'})
 * Transformation status: 33 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMCNTENSET_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMCNTENSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMCNTENSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else
        SPMCNTENSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   !ELIsInHost(EL0)
    //              &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMCNTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMCNTENSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMCNTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMCNTENSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMCNTENSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMCNTENSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
}


/**
 * SPMCNTENCLR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '010'})
 * Transformation status: 33 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMCNTENCLR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMCNTENCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMCNTENCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else
        SPMCNTENCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   !ELIsInHost(EL0)
    //              &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMCNTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMCNTENCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMCNTEN == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMCNTENCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMCNTENCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMCNTENCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
}


/**
 * SPMOVSCLR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '011'})
 * Transformation status: 33 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMOVSCLR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMOVSCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMOVSCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else
        SPMOVSCLR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   !ELIsInHost(EL0)
    //              &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMOVS == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMOVSCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMOVS == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMOVSCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMOVSCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMOVSCLR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
}


/**
 * SPMZR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '100'})
 * Transformation status: 33 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMZR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMZR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMZR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else
        SPMZR_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   !ELIsInHost(EL0)
    //              &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMEVCNTRn_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMZR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMEVCNTRn_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMZR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMZR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMZR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
}


/**
 * SPMSELR_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMSELR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,5),
                                     "SPMSELR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,5),
                                     "SPMSELR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,5), "SPMSELR_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMSELR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMSELR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMSELR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMSELR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMSELR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMSELR_EL0 = X<t,0x40>;
}


/**
 * SPMOVSSET_EL0 - OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1001', 'CRm': '1110', 'op2': '011'})
 * Transformation status: 33 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMOVSSET_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(pVCpu->cpum.GstCtx.Mdscr.u64 & RT_BIT_64(34)/*EnSPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMOVSSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(15)/*EnSPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
               != 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        SPMOVSSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    }
    else
        SPMOVSSET_EL0<UInt(AArch64.SPMSELR_EL0.SYSPMUSEL)> = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (AArch64.MDSCR_EL1.EnSPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   !ELIsInHost(EL0)
    //              &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMOVS == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMOVSSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMOVS == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMOVSSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMOVSSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMOVSSET_EL0<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
}


/**
 * DBGVCR32_EL2 - OrderedDict({'op0': '10', 'op1': '100', 'CRn': '0000', 'CRm': '0111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_DBGVCR32_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAa32El1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,0,7,0), "DBGVCR32_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         DBGVCR32_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     DBGVCR32_EL2 = X<t,0x40>;
}


/**
 * BRBCR_EL2 - OrderedDict({'op0': '10', 'op1': '100', 'CRn': '1001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_BRBCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,0,0), "BRBCR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRBCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     BRBCR_EL2 = X<t,0x40>;
}


/**
 * SPMACCESSR_EL2 - OrderedDict({'op0': '10', 'op1': '100', 'CRn': '1001', 'CRm': '1101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMACCESSR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,13,3), "SPMACCESSR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMACCESSR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMACCESSR_EL2 = X<t,0x40>;
}


/**
 * BRBCR_EL12 - OrderedDict({'op0': '10', 'op1': '101', 'CRn': '1001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_BRBCR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x8e0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,0), "BRBCR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x8e0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             BRBCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         BRBCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * SPMACCESSR_EL12 - OrderedDict({'op0': '10', 'op1': '101', 'CRn': '1001', 'CRm': '1101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMACCESSR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpmu)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x8e8, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,3),
                                     "SPMACCESSR_EL1",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x8e8> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             SPMACCESSR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         SPMACCESSR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * SPMACCESSR_EL3 - OrderedDict({'op0': '10', 'op1': '110', 'CRn': '1001', 'CRm': '1101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMACCESSR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPMU))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     SPMACCESSR_EL3 = X<t,0x40>;
}


/**
 * SPMROOTCR_EL3 - OrderedDict({'op0': '10', 'op1': '110', 'CRn': '1001', 'CRm': '1110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMROOTCR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_RME) && IsFeatureImplemented(FEAT_SPMU)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.SPMROOTCR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMROOTCR_EL3<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
}


/**
 * SPMSCR_EL1 - OrderedDict({'op0': '10', 'op1': '111', 'CRn': '1001', 'CRm': '1110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPMSCR_EL1(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveELUsingSecurityState(EL1, true) && IsFeatureImplemented(FEAT_SPMU)))
    //     Undefined()
    // else if (IsCurrentSecurityState(SS_NonSecure) || (IsFeatureImplemented(FEAT_RME) && IsCurrentSecurityState(SS_Realm)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMSCR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMSCR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
    //                 != '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SPMSCR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPMSCR_EL1<UInt(SPMSELR_EL0.SYSPMUSEL)> = X<t,0x40>;
}


/**
 * SCTLR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x110, uValue);
        if (pGstFeats->fSrMask)
            pVCpu->cpum.GstCtx.Sctlr.u64 = (  (uValue & ~iemGetEffSctlrMaskEl1(pVCpu, pGstFeats))
                                            | (pVCpu->cpum.GstCtx.Sctlr.u64 & iemGetEffSctlrMaskEl1(pVCpu, pGstFeats)) );
        else
            pVCpu->cpum.GstCtx.Sctlr.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        {
            if (pGstFeats->fSrMask)
                pVCpu->cpum.GstCtx.SctlrEl2.u64 = (  (uValue & ~iemGetEffSctlrMaskEl1(pVCpu, pGstFeats))
                                                   | (pVCpu->cpum.GstCtx.SctlrEl2.u64 & iemGetEffSctlrMaskEl1(pVCpu, pGstFeats)) );
            else
                pVCpu->cpum.GstCtx.SctlrEl2.u64 = uValue;
        }
        else
            pVCpu->cpum.GstCtx.Sctlr.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.SCTLR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x110> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         SCTLR_EL1 = (X<t,0x40> AND NOT EffectiveSCTLRMASK_EL1()) OR (SCTLR_EL1 AND EffectiveSCTLRMASK_EL1());
    //     else
    //         SCTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             SCTLR_EL2 = (X<t,0x40> AND NOT EffectiveSCTLRMASK_EL2()) OR (SCTLR_EL2 AND EffectiveSCTLRMASK_EL2());
    //         else
    //             SCTLR_EL2 = X<t,0x40>;
    //     else
    //         SCTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCTLR_EL1 = X<t,0x40>;
}


/**
 * ACTLR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ACTLR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(21)/*TACR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x118, uValue);
        if (pGstFeats->fSrMask)
            pVCpu->cpum.GstCtx.Actlr.u64 = (  (uValue & ~iemGetEffActlrMaskEl1(pVCpu, pGstFeats))
                                            | (pVCpu->cpum.GstCtx.Actlr.u64 & iemGetEffActlrMaskEl1(pVCpu, pGstFeats)) );
        else
            pVCpu->cpum.GstCtx.Actlr.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Actlr.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TACR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EffectiveHCR_EL2_NVx() IN ('1x1')
    //              && (!ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") || EffectiveHCR_EL2_NVx() == '111'))
    //         NVMem<0x118> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         ACTLR_EL1 = (X<t,0x40> AND NOT EffectiveACTLRMASK_EL1()) OR (ACTLR_EL1 AND EffectiveACTLRMASK_EL1());
    //     else
    //         ACTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") && ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             ACTLR_EL2 = (X<t,0x40> AND NOT EffectiveACTLRMASK_EL2()) OR (ACTLR_EL2 AND EffectiveACTLRMASK_EL2());
    //         else
    //             ACTLR_EL2 = X<t,0x40>;
    //     else
    //         ACTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ACTLR_EL1 = X<t,0x40>;
}


/**
 * CPACR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CPACR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(31)/*TCPAC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x100, uValue);
        if (pGstFeats->fSrMask)
            pVCpu->cpum.GstCtx.Cpacr.u64 = (  (uValue & ~iemGetEffCpacrMaskEl1(pVCpu, pGstFeats))
                                            | (pVCpu->cpum.GstCtx.Cpacr.u64 & iemGetEffCpacrMaskEl1(pVCpu, pGstFeats)) );
        else
            pVCpu->cpum.GstCtx.Cpacr.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        {
            if (pGstFeats->fSrMask)
                pVCpu->cpum.GstCtx.CptrEl2.u64 = (  (uValue & ~iemGetEffCptrMaskEl2(pVCpu, pGstFeats))
                                                  | (pVCpu->cpum.GstCtx.CptrEl2.u64 & iemGetEffCptrMaskEl2(pVCpu, pGstFeats)) );
            else
                pVCpu->cpum.GstCtx.CptrEl2.u64 = uValue;
        }
        else
            pVCpu->cpum.GstCtx.Cpacr.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TCPAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.CPACR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x100> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         CPACR_EL1 = (X<t,0x40> AND NOT EffectiveCPACRMASK_EL1()) OR (CPACR_EL1 AND EffectiveCPACRMASK_EL1());
    //     else
    //         CPACR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             CPTR_EL2 = (X<t,0x40> AND NOT EffectiveCPTRMASK_EL2()) OR (CPTR_EL2 AND EffectiveCPTRMASK_EL2());
    //         else
    //             CPTR_EL2 = X<t,0x40>;
    //     else
    //         CPACR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CPACR_EL1 = X<t,0x40>;
}


/**
 * SCTLR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 6 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR2_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSctlr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x278, uValue);
        if (pGstFeats->fSrMask)
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3),
                                         "SCTLR2_EL1",
                                         (uValue & ~EffectiveSCTLR2MASK_EL1()) | (SCTLR2_EL1 & EffectiveSCTLR2MASK_EL1()),
                                         uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3), "SCTLR2_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if (pGstFeats->fSrMask)
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,3),
                                         "SCTLR2_EL2",
                                         (uValue & ~EffectiveSCTLR2MASK_EL2()) | (SCTLR2_EL2 & EffectiveSCTLR2MASK_EL2()),
                                         uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,3), "SCTLR2_EL2", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3), "SCTLR2_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SCTLR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.SCTLR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SCTLR2En == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x278> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         SCTLR2_EL1 = (X<t,0x40> AND NOT EffectiveSCTLR2MASK_EL1()) OR (SCTLR2_EL1 AND EffectiveSCTLR2MASK_EL1());
    //     else
    //         SCTLR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             SCTLR2_EL2 = (X<t,0x40> AND NOT EffectiveSCTLR2MASK_EL2()) OR (SCTLR2_EL2 AND EffectiveSCTLR2MASK_EL2());
    //         else
    //             SCTLR2_EL2 = X<t,0x40>;
    //     else
    //         SCTLR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCTLR2_EL1 = X<t,0x40>;
}


/**
 * RGSR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_RGSR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(56)/*ATA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,5), "RGSR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,5), "RGSR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.ATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         RGSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         RGSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     RGSR_EL1 = X<t,0x40>;
}


/**
 * GCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(56)/*ATA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,6), "GCR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,6), "GCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.ATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     GCR_EL1 = X<t,0x40>;
}


/**
 * ZCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ZCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSve)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 16) & UINT32_C(0x3)/*ZEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSve(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(8)/*TZ*/))
            return iemRaiseSystemAccessTrapSve(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 16) & UINT32_C(0x3)/*ZEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSve(pVCpu, 2);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1e0, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,0), "ZCR_EL1", uValue, uInstrEssence);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(8)/*TZ*/))
        return iemRaiseSystemAccessTrapSve(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 16) & UINT32_C(0x3)/*ZEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapSve(pVCpu, 2);
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,0), "ZCR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,0), "ZCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SVE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.EZ == '0')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.ZEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 0x19)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.ZEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.EZ == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x19)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x1e0> = X<t,0x40>;
    //     else
    //         ZCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.EZ == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.ZEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.EZ == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x19)
    //     else if (ELIsInHost(EL2))
    //         ZCR_EL2 = X<t,0x40>;
    //     else
    //         ZCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.EZ == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x19)
    //     else
    //         ZCR_EL1 = X<t,0x40>;
}


/**
 * TRFCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRFCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrf)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(19)/*TTRF*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x880, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,1), "TRFCR_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,1), "TRFCR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,1), "TRFCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRF))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TTRF == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRFCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TTRF == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TTRF == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x880> = X<t,0x40>;
    //     else
    //         TRFCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TTRF == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TTRF == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         TRFCR_EL2 = X<t,0x40>;
    //     else
    //         TRFCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TRFCR_EL1 = X<t,0x40>;
}


/**
 * TRCITECR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCITECR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fIte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x888, uValue);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,3),
                                     "TRCITECR_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,3),
                                     "TRCITECR_EL2",
                                     uValue,
                                     uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,3), "TRCITECR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ITE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnITE == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nTRCITECR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnITE == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x888> = X<t,0x40>;
    //     else
    //         TRCITECR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnITE == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnITE == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         TRCITECR_EL2 = X<t,0x40>;
    //     else
    //         TRCITECR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TRCITECR_EL1 = X<t,0x40>;
}


/**
 * SMPRI_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SMPRI_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,4), "SMPRI_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,4), "SMPRI_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nSMPRI_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SMPRI_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SMPRI_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SMPRI_EL1 = X<t,0x40>;
}


/**
 * SMCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SMCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1f0, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,6), "SMCR_EL1", uValue, uInstrEssence);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,6), "SMCR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,6), "SMCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 0x1d)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x1f0> = X<t,0x40>;
    //     else
    //         SMCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else if (ELIsInHost(EL2))
    //         SMCR_EL2 = X<t,0x40>;
    //     else
    //         SMCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         SMCR_EL1 = X<t,0x40>;
}


/**
 * SCTLRMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLRMASK_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x318, uValue);
        if (iemGetEffSctlrMaskEl1(pVCpu, pGstFeats))
            return iemRaiseUndefined(pVCpu);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,0),
                                     "SCTLRMASK_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if (iemGetEffSctlrMaskEl1(pVCpu, pGstFeats))
            return iemRaiseUndefined(pVCpu);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,0),
                                     "SCTLRMASK_EL2",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,0), "SCTLRMASK_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nSCTLRMASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x318> = X<t,0x40>;
    //     else if (!IsZero(EffectiveSCTLRMASK_EL1()))
    //         Undefined()
    //     else
    //         SCTLRMASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         if (!IsZero(EffectiveSCTLRMASK_EL2()))
    //             Undefined()
    //         else
    //             SCTLRMASK_EL2 = X<t,0x40>;
    //     else
    //         SCTLRMASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCTLRMASK_EL1 = X<t,0x40>;
}


/**
 * ACTLRMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 2 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ACTLRMASK_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            uValue = NVMem<0x340>;
        else if (iemGetEffActlrMaskEl1(pVCpu, pGstFeats))
            return iemRaiseUndefined(pVCpu);
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,1),
                                         "ACTLRMASK_EL1",
                                         uValue,
                                         uInstrEssence);
    }
    else
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,1),
                                     "ACTLRMASK_EL1",
                                     uValue,
                                     uInstrEssence);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nACTLRMASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   EffectiveHCR_EL2_NVx() IN ('1x1')
    //              && (!ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") || EffectiveHCR_EL2_NVx() == '111'))
    //         X<t,0x40> = NVMem<0x340>;
    //     else if (!IsZero(EffectiveACTLRMASK_EL1()))
    //         Undefined()
    //     else
    //         ACTLRMASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") && ELIsInHost(EL2))
    //         if (!IsZero(EffectiveACTLRMASK_EL2()))
    //             Undefined()
    //         else
    //             ACTLRMASK_EL2 = X<t,0x40>;
    //     else
    //         ACTLRMASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ACTLRMASK_EL1 = X<t,0x40>;
}


/**
 * CPACRMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CPACRMASK_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x320, uValue);
        if (iemGetEffCpacrMaskEl1(pVCpu, pGstFeats))
            return iemRaiseUndefined(pVCpu);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,2),
                                     "CPACRMASK_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if (iemGetEffCptrMaskEl2(pVCpu, pGstFeats))
            return iemRaiseUndefined(pVCpu);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,2),
                                     "CPTRMASK_EL2",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,2), "CPACRMASK_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nCPACRMASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x320> = X<t,0x40>;
    //     else if (!IsZero(EffectiveCPACRMASK_EL1()))
    //         Undefined()
    //     else
    //         CPACRMASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         if (!IsZero(EffectiveCPTRMASK_EL2()))
    //             Undefined()
    //         else
    //             CPTRMASK_EL2 = X<t,0x40>;
    //     else
    //         CPACRMASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CPACRMASK_EL1 = X<t,0x40>;
}


/**
 * SCTLR2MASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 2 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR2MASK_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x328, uValue);
        if (EffectiveSCTLR2MASK_EL1())
            return iemRaiseUndefined(pVCpu);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,3),
                                     "SCTLR2MASK_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if (EffectiveSCTLR2MASK_EL2())
            return iemRaiseUndefined(pVCpu);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,3),
                                     "SCTLR2MASK_EL2",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,3), "SCTLR2MASK_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nSCTLR2MASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x328> = X<t,0x40>;
    //     else if (!IsZero(EffectiveSCTLR2MASK_EL1()))
    //         Undefined()
    //     else
    //         SCTLR2MASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         if (!IsZero(EffectiveSCTLR2MASK_EL2()))
    //             Undefined()
    //         else
    //             SCTLR2MASK_EL2 = X<t,0x40>;
    //     else
    //         SCTLR2MASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCTLR2MASK_EL1 = X<t,0x40>;
}


/**
 * CPACRALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CPACRALIAS_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(31)/*TCPAC*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x100, uValue);
        if (pGstFeats->fSrMask)
            pVCpu->cpum.GstCtx.Cpacr.u64 = (  (uValue & ~iemGetEffCpacrMaskEl1(pVCpu, pGstFeats))
                                            | (pVCpu->cpum.GstCtx.Cpacr.u64 & iemGetEffCpacrMaskEl1(pVCpu, pGstFeats)) );
        else
            pVCpu->cpum.GstCtx.Cpacr.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        {
            if (pGstFeats->fSrMask)
                pVCpu->cpum.GstCtx.CptrEl2.u64 = (  (uValue & ~iemGetEffCptrMaskEl2(pVCpu, pGstFeats))
                                                  | (pVCpu->cpum.GstCtx.CptrEl2.u64 & iemGetEffCptrMaskEl2(pVCpu, pGstFeats)) );
            else
                pVCpu->cpum.GstCtx.CptrEl2.u64 = uValue;
        }
        else
            pVCpu->cpum.GstCtx.Cpacr.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TCPAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nCPACRALIAS_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x100> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         CPACR_EL1 = (X<t,0x40> AND NOT EffectiveCPACRMASK_EL1()) OR (CPACR_EL1 AND EffectiveCPACRMASK_EL1());
    //     else
    //         CPACR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             CPTR_EL2 = (X<t,0x40> AND NOT EffectiveCPTRMASK_EL2()) OR (CPTR_EL2 AND EffectiveCPTRMASK_EL2());
    //         else
    //             CPTR_EL2 = X<t,0x40>;
    //     else
    //         CPACR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CPACR_EL1 = X<t,0x40>;
}


/**
 * ACTLRALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ACTLRALIAS_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(21)/*TACR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x118, uValue);
        if (pGstFeats->fSrMask)
            pVCpu->cpum.GstCtx.Actlr.u64 = (  (uValue & ~iemGetEffActlrMaskEl1(pVCpu, pGstFeats))
                                            | (pVCpu->cpum.GstCtx.Actlr.u64 & iemGetEffActlrMaskEl1(pVCpu, pGstFeats)) );
        else
            pVCpu->cpum.GstCtx.Actlr.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Actlr.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TACR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nACTLRALIAS_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EffectiveHCR_EL2_NVx() IN ('1x1')
    //              && (!ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") || EffectiveHCR_EL2_NVx() == '111'))
    //         NVMem<0x118> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         ACTLR_EL1 = (X<t,0x40> AND NOT EffectiveACTLRMASK_EL1()) OR (ACTLR_EL1 AND EffectiveACTLRMASK_EL1());
    //     else
    //         ACTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ImpDefBool("IMPLEMENTED_ACTLR_ELx accessor behavior") && ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             ACTLR_EL2 = (X<t,0x40> AND NOT EffectiveACTLRMASK_EL2()) OR (ACTLR_EL2 AND EffectiveACTLRMASK_EL2());
    //         else
    //             X<t,0x40> = ACTLR_EL2;
    //     else
    //         ACTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ACTLR_EL1 = X<t,0x40>;
}


/**
 * SCTLRALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLRALIAS_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x110, uValue);
        if (pGstFeats->fSrMask)
            pVCpu->cpum.GstCtx.Sctlr.u64 = (  (uValue & ~iemGetEffSctlrMaskEl1(pVCpu, pGstFeats))
                                            | (pVCpu->cpum.GstCtx.Sctlr.u64 & iemGetEffSctlrMaskEl1(pVCpu, pGstFeats)) );
        else
            pVCpu->cpum.GstCtx.Sctlr.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        {
            if (pGstFeats->fSrMask)
                pVCpu->cpum.GstCtx.SctlrEl2.u64 = (  (uValue & ~iemGetEffSctlrMaskEl1(pVCpu, pGstFeats))
                                                   | (pVCpu->cpum.GstCtx.SctlrEl2.u64 & iemGetEffSctlrMaskEl1(pVCpu, pGstFeats)) );
            else
                pVCpu->cpum.GstCtx.SctlrEl2.u64 = uValue;
        }
        else
            pVCpu->cpum.GstCtx.Sctlr.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nSCTLRALIAS_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x110> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         SCTLR_EL1 = (X<t,0x40> AND NOT EffectiveSCTLRMASK_EL1()) OR (SCTLR_EL1 AND EffectiveSCTLRMASK_EL1());
    //     else
    //         SCTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             SCTLR_EL2 = (X<t,0x40> AND NOT EffectiveSCTLRMASK_EL2()) OR (SCTLR_EL2 AND EffectiveSCTLRMASK_EL2());
    //         else
    //             SCTLR_EL2 = X<t,0x40>;
    //     else
    //         SCTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCTLR_EL1 = X<t,0x40>;
}


/**
 * SCTLR2ALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0001', 'CRm': '0100', 'op2': '111'})
 * Transformation status: 6 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR2ALIAS_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSctlr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x278, uValue);
        if (pGstFeats->fSrMask)
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3),
                                         "SCTLR2_EL1",
                                         (uValue & ~EffectiveSCTLR2MASK_EL1()) | (SCTLR2_EL1 & EffectiveSCTLR2MASK_EL1()),
                                         uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3), "SCTLR2_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if (pGstFeats->fSrMask)
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,3),
                                         "SCTLR2_EL2",
                                         (uValue & ~EffectiveSCTLR2MASK_EL2()) | (SCTLR2_EL2 & EffectiveSCTLR2MASK_EL2()),
                                         uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,3), "SCTLR2_EL2", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3), "SCTLR2_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SCTLR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nSCTLRALIAS2_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SCTLR2En == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x278> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         SCTLR2_EL1 = (X<t,0x40> AND NOT EffectiveSCTLR2MASK_EL1()) OR (SCTLR2_EL1 AND EffectiveSCTLR2MASK_EL1());
    //     else
    //         SCTLR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             SCTLR2_EL2 = (X<t,0x40> AND NOT EffectiveSCTLR2MASK_EL2()) OR (SCTLR2_EL2 AND EffectiveSCTLR2MASK_EL2());
    //         else
    //             SCTLR2_EL2 = X<t,0x40>;
    //     else
    //         SCTLR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCTLR2_EL1 = X<t,0x40>;
}


/**
 * MAIR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MAIR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x140, uValue);
        pVCpu->cpum.GstCtx.Mair.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.MairEl2.u64 = uValue;
        else
            pVCpu->cpum.GstCtx.Mair.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.MAIR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x140> = X<t,0x40>;
    //     else
    //         MAIR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         MAIR_EL2 = X<t,0x40>;
    //     else
    //         MAIR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MAIR_EL1 = X<t,0x40>;
}


/**
 * MAIR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MAIR2_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x280, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,1), "MAIR2_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,1,1), "MAIR2_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,1), "MAIR2_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nMAIR2_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x280> = X<t,0x40>;
    //     else
    //         MAIR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         MAIR2_EL2 = X<t,0x40>;
    //     else
    //         MAIR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MAIR2_EL1 = X<t,0x40>;
}


/**
 * PIRE0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PIRE0_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x290, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,2), "PIRE0_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,2), "PIRE0_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,2), "PIRE0_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nPIRE0_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x290> = X<t,0x40>;
    //     else
    //         PIRE0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         PIRE0_EL2 = X<t,0x40>;
    //     else
    //         PIRE0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PIRE0_EL1 = X<t,0x40>;
}


/**
 * PIR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PIR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x2a0, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,3), "PIR_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,3), "PIR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,3), "PIR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nPIR_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x2a0> = X<t,0x40>;
    //     else
    //         PIR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         PIR_EL2 = X<t,0x40>;
    //     else
    //         PIR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PIR_EL1 = X<t,0x40>;
}


/**
 * POR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_POR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Poe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x2a8, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,4), "POR_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,4), "POR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,4), "POR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nPOR_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x2a8> = X<t,0x40>;
    //     else
    //         POR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         POR_EL2 = X<t,0x40>;
    //     else
    //         POR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     POR_EL1 = X<t,0x40>;
}


/**
 * S2POR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_S2POR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS2Poe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x2b8, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,5), "S2POR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,5), "S2POR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S2POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nS2POR_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x2b8> = X<t,0x40>;
    //     else
    //         S2POR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         S2POR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     S2POR_EL1 = X<t,0x40>;
}


/**
 * AMAIR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMAIR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x148, uValue);
        pVCpu->cpum.GstCtx.Amair.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,0),
                                         "AMAIR_EL2",
                                         uValue,
                                         uInstrEssence);
        pVCpu->cpum.GstCtx.Amair.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.AMAIR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x148> = X<t,0x40>;
    //     else
    //         AMAIR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AMAIR_EL2 = X<t,0x40>;
    //     else
    //         AMAIR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     AMAIR_EL1 = X<t,0x40>;
}


/**
 * AMAIR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMAIR2_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x288, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,3,1), "AMAIR2_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,1), "AMAIR2_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,3,1), "AMAIR2_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nAMAIR2_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x288> = X<t,0x40>;
    //     else
    //         AMAIR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         AMAIR2_EL2 = X<t,0x40>;
    //     else
    //         AMAIR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     AMAIR2_EL1 = X<t,0x40>;
}


/**
 * LORSA_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_LORSA_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fLor)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(35)/*TLOR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,0), "LORSA_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,0), "LORSA_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_LOR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TLOR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.LORSA_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         LORSA_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         LORSA_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else
    //         LORSA_EL1 = X<t,0x40>;
}


/**
 * LOREA_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_LOREA_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fLor)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(35)/*TLOR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,1), "LOREA_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,1), "LOREA_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_LOR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TLOR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.LOREA_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         LOREA_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         LOREA_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else
    //         LOREA_EL1 = X<t,0x40>;
}


/**
 * LORN_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_LORN_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fLor)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(35)/*TLOR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,2), "LORN_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,2), "LORN_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_LOR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TLOR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.LORN_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         LORN_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         LORN_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else
    //         LORN_EL1 = X<t,0x40>;
}


/**
 * LORC_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_LORC_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fLor)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(35)/*TLOR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,3), "LORC_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,3), "LORC_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_LOR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TLOR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.LORC_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         LORC_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TLOR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TLOR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         LORC_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else
    //         LORC_EL1 = X<t,0x40>;
}


/**
 * MPAM1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAM1_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAM2_EL2.TRAPMPAM1EL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x900, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,0), "MPAM1_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,0), "MPAM2_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,0), "MPAM1_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAM2_EL2.TRAPMPAM1EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x900> = X<t,0x40>;
    //     else
    //         MPAM1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         MPAM2_EL2 = X<t,0x40>;
    //     else
    //         MPAM1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAM1_EL1 = X<t,0x40>;
}


/**
 * MPAM0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAM0_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAM2_EL2.TRAPMPAM0EL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,1), "MPAM0_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,1), "MPAM0_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAM2_EL2.TRAPMPAM0EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         MPAM0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAM0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAM0_EL1 = X<t,0x40>;
}


/**
 * MPAMSM_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '011'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMSM_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || !pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAM2_EL2.EnMPAMSM == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,3), "MPAMSM_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,3), "MPAMSM_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && IsFeatureImplemented(FEAT_SME)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAM2_EL2.EnMPAMSM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         MPAMSM_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMSM_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMSM_EL1 = X<t,0x40>;
}


/**
 * MPAMBW1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '100'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMBW1_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAMBW2_EL2.nTRAP_MPAMBW1_EL1 == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x908, uValue);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,4),
                                     "MPAMBW1_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,4),
                                     "MPAMBW2_EL2",
                                     uValue,
                                     uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,4), "MPAMBW1_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAMBW2_EL2.nTRAP_MPAMBW1_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x908> = X<t,0x40>;
    //     else
    //         MPAMBW1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         MPAMBW2_EL2 = X<t,0x40>;
    //     else
    //         MPAMBW1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMBW1_EL1 = X<t,0x40>;
}


/**
 * MPAMBW0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMBW0_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAMBW2_EL2.nTRAP_MPAMBW0_EL1 == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,5),
                                     "MPAMBW0_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,5), "MPAMBW0_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAMBW2_EL2.nTRAP_MPAMBW0_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         MPAMBW0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMBW0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMBW0_EL1 = X<t,0x40>;
}


/**
 * MPAMBWSM_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1010', 'CRm': '0101', 'op2': '111'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMBWSM_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl || !pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.MPAMBW2_EL2.nTRAP_MPAMBWSM_EL1 == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,7),
                                     "MPAMBWSM_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,7), "MPAMBWSM_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) && IsFeatureImplemented(FEAT_SME)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EL2Enabled() && AArch64.MPAMBW2_EL2.nTRAP_MPAMBWSM_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         MPAMBWSM_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMBWSM_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMBWSM_EL1 = X<t,0x40>;
}


/**
 * VBAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VBAR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x250, uValue);
        pVCpu->cpum.GstCtx.VBar.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.VBarEl2.u64 = uValue;
        else
            pVCpu->cpum.GstCtx.VBar.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '011')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.VBAR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x250> = X<t,0x40>;
    //     else
    //         VBAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         VBAR_EL2 = X<t,0x40>;
    //     else
    //         VBAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     VBAR_EL1 = X<t,0x40>;
}


/**
 * RMR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_RMR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1 && !pGstFeats->fEl2)
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,0,2), "RMR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsHighestEL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL1 && IsHighestEL(EL1))
    //     RMR_EL1 = X<t,0x40>;
    // else
    //     Undefined()
}


/**
 * DISR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_DISR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !!(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(5)/*AMO*/))
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,1,1),
                                         "VDISR_EL2",
                                         uValue,
                                         uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,1,1), "DISR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,1,1), "DISR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && (   AArch64.HCR_EL2.AMO == '1'
    //             || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && AArch64.HCRX_EL2.TMEA == '1')))
    //         VDISR_EL2 = X<t,0x40>;
    //     else if (HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && AArch64.SCR_EL3.EnDSE == '1')
    //         VDISR_EL3 = X<t,0x40>;
    //     else if (HaveEL(EL3) && !Halted() && AArch64.SCR_EL3.EA == '1')
    //         return;
    //     else
    //         DISR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && AArch64.SCR_EL3.EnDSE == '1')
    //         VDISR_EL3 = X<t,0x40>;
    //     else if (HaveEL(EL3) && !Halted() && AArch64.SCR_EL3.EA == '1')
    //         return;
    //     else
    //         DISR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     DISR_EL1 = X<t,0x40>;
}


/**
 * ICC_DIR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1011', 'op2': '001'})
 * Transformation status: 6 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_DIR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TDIR == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TC == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            ICV_DIR_EL1 = uValue;
        else if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            ICV_DIR_EL1 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,1),
                                         "ICC_DIR_EL1",
                                         uValue,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,1),
                                     "ICC_DIR_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TDIR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         ICV_DIR_EL1 = X<t,0x40>;
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         ICV_DIR_EL1 = X<t,0x40>;
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_DIR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_DIR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_DIR_EL1 = X<t,0x40>;
}


/**
 * ICC_SGI1R_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1011', 'op2': '101'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_SGI1R_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TC == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,5),
                                     "ICC_SGI1R_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    if (AArch64.ICC_SRE_EL2.SRE == 0)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,5), "ICC_SGI1R_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_SGI1R_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_SGI1R_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_SGI1R_EL1 = X<t,0x40>;
}


/**
 * ICC_ASGI1R_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1011', 'op2': '110'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_ASGI1R_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TC == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,6),
                                     "ICC_ASGI1R_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    if (AArch64.ICC_SRE_EL2.SRE == 0)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu,
                                 ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,6),
                                 "ICC_ASGI1R_EL1",
                                 uValue,
                                 uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_ASGI1R_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_ASGI1R_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_ASGI1R_EL1 = X<t,0x40>;
}


/**
 * ICC_SGI0R_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1011', 'op2': '111'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_SGI0R_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TC == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,7),
                                     "ICC_SGI0R_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    if (AArch64.ICC_SRE_EL2.SRE == 0)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,7), "ICC_SGI0R_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_SGI0R_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_SGI0R_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_SGI0R_EL1 = X<t,0x40>;
}


/**
 * ICC_EOIR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '001'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_EOIR1_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            ICV_EOIR1_EL1 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,1),
                                         "ICC_EOIR1_EL1",
                                         uValue,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,1),
                                     "ICC_EOIR1_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         ICV_EOIR1_EL1 = X<t,0x40>;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_EOIR1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_EOIR1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_EOIR1_EL1 = X<t,0x40>;
}


/**
 * ICC_BPR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '011'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_BPR1_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            ICV_BPR1_EL1 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,3),
                                         "ICC_BPR1_EL1",
                                         uValue,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,3),
                                     "ICC_BPR1_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         ICV_BPR1_EL1 = X<t,0x40>;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             ICC_BPR1_EL1_S = X<t,0x40>;
    //         else
    //             ICC_BPR1_EL1_NS = X<t,0x40>;
    //     else
    //         ICC_BPR1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             ICC_BPR1_EL1_S = X<t,0x40>;
    //         else
    //             ICC_BPR1_EL1_NS = X<t,0x40>;
    //     else
    //         ICC_BPR1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.SCR_EL3.NS == '0')
    //         ICC_BPR1_EL1_S = X<t,0x40>;
    //     else
    //         ICC_BPR1_EL1_NS = X<t,0x40>;
}


/**
 * ICC_CTLR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '100'})
 * Transformation status: 5 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_CTLR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TC == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            ICV_CTLR_EL1 = uValue;
        else if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            ICV_CTLR_EL1 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,4),
                                         "ICC_CTLR_EL1",
                                         uValue,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,4),
                                     "ICC_CTLR_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         ICV_CTLR_EL1 = X<t,0x40>;
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         ICV_CTLR_EL1 = X<t,0x40>;
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             ICC_CTLR_EL1_S = X<t,0x40>;
    //         else
    //             ICC_CTLR_EL1_NS = X<t,0x40>;
    //     else
    //         ICC_CTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             ICC_CTLR_EL1_S = X<t,0x40>;
    //         else
    //             ICC_CTLR_EL1_NS = X<t,0x40>;
    //     else
    //         ICC_CTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.SCR_EL3.NS == '0')
    //         ICC_CTLR_EL1_S = X<t,0x40>;
    //     else
    //         ICC_CTLR_EL1_NS = X<t,0x40>;
}


/**
 * ICC_SRE_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '101'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_SRE_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && AArch64.ICC_SRE_EL2.Enable == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,5),
                                     "ICC_SRE_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,5), "ICC_SRE_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.ICC_SRE_EL3.Enable == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.ICC_SRE_EL2.Enable == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.ICC_SRE_EL3.Enable == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             ICC_SRE_EL1_S = X<t,0x40>;
    //         else
    //             ICC_SRE_EL1_NS = X<t,0x40>;
    //     else
    //         ICC_SRE_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.ICC_SRE_EL3.Enable == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.ICC_SRE_EL3.Enable == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             ICC_SRE_EL1_S = X<t,0x40>;
    //         else
    //             ICC_SRE_EL1_NS = X<t,0x40>;
    //     else
    //         ICC_SRE_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.NS == '0')
    //         ICC_SRE_EL1_S = X<t,0x40>;
    //     else
    //         ICC_SRE_EL1_NS = X<t,0x40>;
}


/**
 * ICC_IGRPEN0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '110'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_IGRPEN0_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL0 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            ICV_IGRPEN0_EL1 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,6),
                                         "ICC_IGRPEN0_EL1",
                                         uValue,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,6),
                                     "ICC_IGRPEN0_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ICC_IGRPENn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         ICV_IGRPEN0_EL1 = X<t,0x40>;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_IGRPEN0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_IGRPEN0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_IGRPEN0_EL1 = X<t,0x40>;
}


/**
 * ICC_IGRPEN1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1100', 'op2': '111'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_IGRPEN1_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL1 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            ICV_IGRPEN1_EL1 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,7),
                                         "ICC_IGRPEN1_EL1",
                                         uValue,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,7),
                                     "ICC_IGRPEN1_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ICC_IGRPENn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         ICV_IGRPEN1_EL1 = X<t,0x40>;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             ICC_IGRPEN1_EL1_S = X<t,0x40>;
    //         else
    //             ICC_IGRPEN1_EL1_NS = X<t,0x40>;
    //     else
    //         ICC_IGRPEN1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3))
    //         if (AArch64.SCR_EL3.NS == '0')
    //             ICC_IGRPEN1_EL1_S = X<t,0x40>;
    //         else
    //             ICC_IGRPEN1_EL1_NS = X<t,0x40>;
    //     else
    //         ICC_IGRPEN1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.SCR_EL3.NS == '0')
    //         ICC_IGRPEN1_EL1_S = X<t,0x40>;
    //     else
    //         ICC_IGRPEN1_EL1_NS = X<t,0x40>;
}


/**
 * ICC_EOIR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1000', 'op2': '001'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_EOIR0_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL0 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            ICV_EOIR0_EL1 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,1),
                                         "ICC_EOIR0_EL1",
                                         uValue,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,1),
                                     "ICC_EOIR0_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         ICV_EOIR0_EL1 = X<t,0x40>;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_EOIR0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_EOIR0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_EOIR0_EL1 = X<t,0x40>;
}


/**
 * ICC_BPR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1000', 'op2': '011'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_BPR0_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TALL0 == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            ICV_BPR0_EL1 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,3),
                                         "ICC_BPR0_EL1",
                                         uValue,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,3),
                                     "ICC_BPR0_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         ICV_BPR0_EL1 = X<t,0x40>;
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_BPR0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_BPR0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_BPR0_EL1 = X<t,0x40>;
}


/**
 * CONTEXTIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CONTEXTIDR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x108, uValue);
        pVCpu->cpum.GstCtx.ContextIdr.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,1),
                                         "CONTEXTIDR_EL2",
                                         uValue,
                                         uInstrEssence);
        pVCpu->cpum.GstCtx.ContextIdr.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.CONTEXTIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x108> = X<t,0x40>;
    //     else
    //         CONTEXTIDR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         CONTEXTIDR_EL2 = X<t,0x40>;
    //     else
    //         CONTEXTIDR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CONTEXTIDR_EL1 = X<t,0x40>;
}


/**
 * RCWSMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_RCWSMASK_EL1(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fThe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    RCWSMASK_EL1<[0x3f:0]> = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_THE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nRCWSMASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         RCWSMASK_EL1<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         RCWSMASK_EL1<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     RCWSMASK_EL1<[0x3f:0]> = X<t,0x40>;
}


/**
 * TPIDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TPIDR_EL1(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        pVCpu->cpum.GstCtx.aTpIdr[1].u64 = uValue;
    else
        pVCpu->cpum.GstCtx.aTpIdr[1].u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGWTR_EL2.TPIDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         TPIDR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     TPIDR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TPIDR_EL1 = X<t,0x40>;
}


/**
 * ACCDATA_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ACCDATA_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fLs64Accdata)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,5),
                                     "ACCDATA_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,5), "ACCDATA_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_LS64_ACCDATA))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ADEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nACCDATA_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ADEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ACCDATA_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ADEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ADEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ACCDATA_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ACCDATA_EL1 = X<t,0x40>;
}


/**
 * RCWMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 6 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_RCWMASK_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fThe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        RCWMASK_EL1<[0x3f:0]> = uValue;
    }
    else
        RCWMASK_EL1<[0x3f:0]> = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_THE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nRCWMASK_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         RCWMASK_EL1<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         RCWMASK_EL1<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     RCWMASK_EL1<[0x3f:0]> = X<t,0x40>;
}


/**
 * SCXTNUM_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCXTNUM_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fCvs2_2 && !pGstFeats->fCsv21p2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(53)/*EnSCXT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x188, uValue);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,7),
                                     "SCXTNUM_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,7),
                                     "SCXTNUM_EL2",
                                     uValue,
                                     uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,7), "SCXTNUM_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_CSV2_2) || IsFeatureImplemented(FEAT_CSV2_1p2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() == '011')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.EnSCXT == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.SCXTNUM_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x188> = X<t,0x40>;
    //     else
    //         SCXTNUM_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         SCXTNUM_EL2 = X<t,0x40>;
    //     else
    //         SCXTNUM_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCXTNUM_EL1 = X<t,0x40>;
}


/**
 * CNTKCTL_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1110', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTKCTL_EL1(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        pVCpu->cpum.GstCtx.CntKCtl.u64 = uValue;
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.CntHCtlEl2.u64 = CNTHCTL_EL2_VHE(X<t,0x40>);
        else
            pVCpu->cpum.GstCtx.CntKCtl.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     CNTKCTL_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         CNTHCTL_EL2 = CNTHCTL_EL2_VHE(X<t,0x40>);
    //     else
    //         CNTKCTL_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTKCTL_EL1 = X<t,0x40>;
}


/**
 * TTBR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TTBR0_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x200, uValue);
        pVCpu->cpum.GstCtx.Ttbr0.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.Ttbr0El2.u64 = uValue;
        else
            pVCpu->cpum.GstCtx.Ttbr0.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.TTBR0_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x200> = X<t,0x40>;
    //     else
    //         TTBR0_EL1<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         TTBR0_EL2<[0x3f:0]> = X<t,0x40>;
    //     else
    //         TTBR0_EL1<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TTBR0_EL1<[0x3f:0]> = X<t,0x40>;
}


/**
 * TTBR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TTBR1_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x210, uValue);
        pVCpu->cpum.GstCtx.Ttbr1.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.Ttbr1El2.u64 = uValue;
        else
            pVCpu->cpum.GstCtx.Ttbr1.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.TTBR1_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x210> = X<t,0x40>;
    //     else
    //         TTBR1_EL1<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         TTBR1_EL2<[0x3f:0]> = X<t,0x40>;
    //     else
    //         TTBR1_EL1<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TTBR1_EL1<[0x3f:0]> = X<t,0x40>;
}


/**
 * TCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x120, uValue);
        if (pGstFeats->fSrMask)
            pVCpu->cpum.GstCtx.Tcr.u64 = (  (uValue & ~EffectiveTCRMASK_EL1())
                                          | (pVCpu->cpum.GstCtx.Tcr.u64 & EffectiveTCRMASK_EL1()) );
        else
            pVCpu->cpum.GstCtx.Tcr.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        {
            if (pGstFeats->fSrMask)
                pVCpu->cpum.GstCtx.TcrEl2.u64 = (  (uValue & ~EffectiveTCRMASK_EL2())
                                                 | (pVCpu->cpum.GstCtx.TcrEl2.u64 & EffectiveTCRMASK_EL2()) );
            else
                pVCpu->cpum.GstCtx.TcrEl2.u64 = uValue;
        }
        else
            pVCpu->cpum.GstCtx.Tcr.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.TCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x120> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         TCR_EL1 = (X<t,0x40> AND NOT EffectiveTCRMASK_EL1()) OR (TCR_EL1 AND EffectiveTCRMASK_EL1());
    //     else
    //         TCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             TCR_EL2 = (X<t,0x40> AND NOT EffectiveTCRMASK_EL2()) OR (TCR_EL2 AND EffectiveTCRMASK_EL2());
    //         else
    //             TCR_EL2 = X<t,0x40>;
    //     else
    //         TCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TCR_EL1 = X<t,0x40>;
}


/**
 * TCR2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 6 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCR2_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTcr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x270, uValue);
        if (pGstFeats->fSrMask)
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3),
                                         "TCR2_EL1",
                                         (uValue & ~EffectiveTCR2MASK_EL1()) | (TCR2_EL1 & EffectiveTCR2MASK_EL1()),
                                         uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3), "TCR2_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if (pGstFeats->fSrMask)
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,3),
                                         "TCR2_EL2",
                                         (uValue & ~EffectiveTCR2MASK_EL2()) | (TCR2_EL2 & EffectiveTCR2MASK_EL2()),
                                         uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,3), "TCR2_EL2", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3), "TCR2_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TCR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.TCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.TCR2En == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x270> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         TCR2_EL1 = (X<t,0x40> AND NOT EffectiveTCR2MASK_EL1()) OR (TCR2_EL1 AND EffectiveTCR2MASK_EL1());
    //     else
    //         TCR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             TCR2_EL2 = (X<t,0x40> AND NOT EffectiveTCR2MASK_EL2()) OR (TCR2_EL2 AND EffectiveTCR2MASK_EL2());
    //         else
    //             TCR2_EL2 = X<t,0x40>;
    //     else
    //         TCR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TCR2_EL1 = X<t,0x40>;
}


/**
 * APIAKeyLo_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_APIAKeyLo_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.Apia.Low.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Apia.Low.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.APIAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APIAKeyLo_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APIAKeyLo_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     APIAKeyLo_EL1 = X<t,0x40>;
}


/**
 * APIAKeyHi_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_APIAKeyHi_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.Apia.High.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Apia.High.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.APIAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APIAKeyHi_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APIAKeyHi_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     APIAKeyHi_EL1 = X<t,0x40>;
}


/**
 * APIBKeyLo_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_APIBKeyLo_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.Apib.Low.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Apib.Low.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.APIBKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APIBKeyLo_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APIBKeyLo_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     APIBKeyLo_EL1 = X<t,0x40>;
}


/**
 * APIBKeyHi_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_APIBKeyHi_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.Apib.High.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Apib.High.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.APIBKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APIBKeyHi_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APIBKeyHi_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     APIBKeyHi_EL1 = X<t,0x40>;
}


/**
 * APDAKeyLo_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_APDAKeyLo_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.Apda.Low.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Apda.Low.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.APDAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APDAKeyLo_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APDAKeyLo_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     APDAKeyLo_EL1 = X<t,0x40>;
}


/**
 * APDAKeyHi_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_APDAKeyHi_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.Apda.High.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Apda.High.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.APDAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APDAKeyHi_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APDAKeyHi_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     APDAKeyHi_EL1 = X<t,0x40>;
}


/**
 * APDBKeyLo_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_APDBKeyLo_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.Apdb.Low.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Apdb.Low.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.APDBKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APDBKeyLo_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APDBKeyLo_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     APDBKeyLo_EL1 = X<t,0x40>;
}


/**
 * APDBKeyHi_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_APDBKeyHi_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.Apdb.High.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Apdb.High.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.APDBKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APDBKeyHi_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APDBKeyHi_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     APDBKeyHi_EL1 = X<t,0x40>;
}


/**
 * APGAKeyLo_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_APGAKeyLo_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.Apga.Low.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Apga.Low.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.APGAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APGAKeyLo_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APGAKeyLo_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     APGAKeyLo_EL1 = X<t,0x40>;
}


/**
 * APGAKeyHi_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_APGAKeyHi_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPAuth)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(40)/*APK*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.Apga.High.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Apga.High.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAuth))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.APK == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.APGAKey == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APGAKeyHi_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.APK == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.APK == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         APGAKeyHi_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     APGAKeyHi_EL1 = X<t,0x40>;
}


/**
 * GCSCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GCSCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x8d0, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,0), "GCSCR_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,5,0), "GCSCR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,0), "GCSCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nGCS_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x8d0> = X<t,0x40>;
    //     else
    //         GCSCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         GCSCR_EL2 = X<t,0x40>;
    //     else
    //         GCSCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     GCSCR_EL1 = X<t,0x40>;
}


/**
 * GCSPR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GCSPR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x8c0, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,1), "GCSPR_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,5,1), "GCSPR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,1), "GCSPR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nGCS_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x8c0> = X<t,0x40>;
    //     else
    //         GCSPR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         GCSPR_EL2 = X<t,0x40>;
    //     else
    //         GCSPR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     GCSPR_EL1 = X<t,0x40>;
}


/**
 * GCSCRE0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0101', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GCSCRE0_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,2), "GCSCRE0_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,2), "GCSCRE0_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nGCS_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GCSCRE0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GCSCRE0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     GCSCRE0_EL1 = X<t,0x40>;
}


/**
 * TCRMASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0111', 'op2': '010'})
 * Transformation status: 2 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCRMASK_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x330, uValue);
        if (EffectiveTCRMASK_EL1())
            return iemRaiseUndefined(pVCpu);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,2), "TCRMASK_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if (EffectiveTCRMASK_EL2())
            return iemRaiseUndefined(pVCpu);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,2), "TCRMASK_EL2", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,2), "TCRMASK_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nTCRMASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x330> = X<t,0x40>;
    //     else if (!IsZero(EffectiveTCRMASK_EL1()))
    //         Undefined()
    //     else
    //         TCRMASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         if (!IsZero(EffectiveTCRMASK_EL2()))
    //             Undefined()
    //         else
    //             TCRMASK_EL2 = X<t,0x40>;
    //     else
    //         TCRMASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TCRMASK_EL1 = X<t,0x40>;
}


/**
 * TCR2MASK_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 2 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCR2MASK_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x338, uValue);
        if (EffectiveTCR2MASK_EL1())
            return iemRaiseUndefined(pVCpu);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,3),
                                     "TCR2MASK_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if (EffectiveTCR2MASK_EL2())
            return iemRaiseUndefined(pVCpu);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,3),
                                     "TCR2MASK_EL2",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,3), "TCR2MASK_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nTCR2MASK_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.SRMASKEn == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x338> = X<t,0x40>;
    //     else if (!IsZero(EffectiveTCR2MASK_EL1()))
    //         Undefined()
    //     else
    //         TCR2MASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         if (!IsZero(EffectiveTCR2MASK_EL2()))
    //             Undefined()
    //         else
    //             TCR2MASK_EL2 = X<t,0x40>;
    //     else
    //         TCR2MASK_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TCR2MASK_EL1 = X<t,0x40>;
}


/**
 * TCRALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0111', 'op2': '110'})
 * Transformation status: 4 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCRALIAS_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x120, uValue);
        if (pGstFeats->fSrMask)
            pVCpu->cpum.GstCtx.Tcr.u64 = (  (uValue & ~EffectiveTCRMASK_EL1())
                                          | (pVCpu->cpum.GstCtx.Tcr.u64 & EffectiveTCRMASK_EL1()) );
        else
            pVCpu->cpum.GstCtx.Tcr.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        {
            if (pGstFeats->fSrMask)
                pVCpu->cpum.GstCtx.TcrEl2.u64 = (  (uValue & ~EffectiveTCRMASK_EL2())
                                                 | (pVCpu->cpum.GstCtx.TcrEl2.u64 & EffectiveTCRMASK_EL2()) );
            else
                pVCpu->cpum.GstCtx.TcrEl2.u64 = uValue;
        }
        else
            pVCpu->cpum.GstCtx.Tcr.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nTCRALIAS_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x120> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         TCR_EL1 = (X<t,0x40> AND NOT EffectiveTCRMASK_EL1()) OR (TCR_EL1 AND EffectiveTCRMASK_EL1());
    //     else
    //         TCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             TCR_EL2 = (X<t,0x40> AND NOT EffectiveTCRMASK_EL2()) OR (TCR_EL2 AND EffectiveTCRMASK_EL2());
    //         else
    //             TCR_EL2 = X<t,0x40>;
    //     else
    //         TCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TCR_EL1 = X<t,0x40>;
}


/**
 * TCR2ALIAS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0111', 'op2': '111'})
 * Transformation status: 6 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCR2ALIAS_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTcr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x270, uValue);
        if (pGstFeats->fSrMask)
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3),
                                         "TCR2_EL1",
                                         (uValue & ~EffectiveTCR2MASK_EL1()) | (TCR2_EL1 & EffectiveTCR2MASK_EL1()),
                                         uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3), "TCR2_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if (pGstFeats->fSrMask)
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,3),
                                         "TCR2_EL2",
                                         (uValue & ~EffectiveTCR2MASK_EL2()) | (TCR2_EL2 & EffectiveTCR2MASK_EL2()),
                                         uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,3), "TCR2_EL2", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3), "TCR2_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TCR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nTCR2ALIAS_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.TCR2En == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x270> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         TCR2_EL1 = (X<t,0x40> AND NOT EffectiveTCR2MASK_EL1()) OR (TCR2_EL1 AND EffectiveTCR2MASK_EL1());
    //     else
    //         TCR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_SRMASK))
    //             TCR2_EL2 = (X<t,0x40> AND NOT EffectiveTCR2MASK_EL2()) OR (TCR2_EL2 AND EffectiveTCR2MASK_EL2());
    //         else
    //             TCR2_EL2 = X<t,0x40>;
    //     else
    //         TCR2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TCR2_EL1 = X<t,0x40>;
}


/**
 * SPSR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPSR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/)
            && !((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 3) == 3))
            return iemRaiseExlockException(pVCpu);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x160, uValue);
        pVCpu->cpum.GstCtx.Spsr.u64 = uValue;
    }
    else
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/)
            && pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemRaiseExlockException(pVCpu);
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.SpsrEl2.u64 = uValue;
        else
            pVCpu->cpum.GstCtx.Spsr.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   IsFeatureImplemented(FEAT_GCS)
    //         && GetCurrentEXLOCKEN()
    //         && !Halted()
    //         && PSTATE.EXLOCK == '1'
    //         && !(EffectiveHCR_EL2_NVx() IN ('x11')))
    //         EXLOCKException()
    //     else if (EffectiveHCR_EL2_NVx() == '011')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x160> = X<t,0x40>;
    //     else
    //         SPSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' && ELIsInHost(EL2))
    //         EXLOCKException()
    //     else if (ELIsInHost(EL2))
    //         SPSR_EL2 = X<t,0x40>;
    //     else
    //         SPSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPSR_EL1 = X<t,0x40>;
}


/**
 * ELR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ELR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/)
            && !((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 3) == 3))
            return iemRaiseExlockException(pVCpu);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x230, uValue);
        pVCpu->cpum.GstCtx.Elr.u64 = uValue;
    }
    else
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/)
            && pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemRaiseExlockException(pVCpu);
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.ElrEl2.u64 = uValue;
        else
            pVCpu->cpum.GstCtx.Elr.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   IsFeatureImplemented(FEAT_GCS)
    //         && GetCurrentEXLOCKEN()
    //         && !Halted()
    //         && PSTATE.EXLOCK == '1'
    //         && !(EffectiveHCR_EL2_NVx() IN ('x11')))
    //         EXLOCKException()
    //     else if (EffectiveHCR_EL2_NVx() == '011')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x230> = X<t,0x40>;
    //     else
    //         ELR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' && ELIsInHost(EL2))
    //         EXLOCKException()
    //     else if (ELIsInHost(EL2))
    //         ELR_EL2 = X<t,0x40>;
    //     else
    //         ELR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ELR_EL1 = X<t,0x40>;
}


/**
 * SP_EL0 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SP_EL0(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (!(pVCpu->cpum.GstCtx.fPState & UINT64_C(0x1)/*SP*/))
        return iemRaiseUndefined(pVCpu);
    pVCpu->cpum.GstCtx.aSpReg[0].u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (PSTATE.SP == '0')
    //         Undefined()
    //     else
    //         SP_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (PSTATE.SP == '0')
    //         Undefined()
    //     else
    //         SP_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (PSTATE.SP == '0')
    //         Undefined()
    //     else
    //         SP_EL0 = X<t,0x40>;
}


/**
 * SPSel - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPSel(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xfffffffffffffffe)) | (uValue & 1);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     PSTATE.SP = (X<t,0x40>)<0>;
    // else if (PSTATE.EL == EL2)
    //     PSTATE.SP = (X<t,0x40>)<0>;
    // else if (PSTATE.EL == EL3)
    //     PSTATE.SP = (X<t,0x40>)<0>;
}


/**
 * PAN - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PAN(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPan)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xffffffffffbfffff)) | (uValue & 0x400000);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAN))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     PSTATE.PAN = (X<t,0x40>)<0x16>;
    // else if (PSTATE.EL == EL2)
    //     PSTATE.PAN = (X<t,0x40>)<0x16>;
    // else if (PSTATE.EL == EL3)
    //     PSTATE.PAN = (X<t,0x40>)<0x16>;
}


/**
 * UAO - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_UAO(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fUao)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xffffffffff7fffff)) | (uValue & 0x800000);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_UAO))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     PSTATE.UAO = (X<t,0x40>)<0x17>;
    // else if (PSTATE.EL == EL2)
    //     PSTATE.UAO = (X<t,0x40>)<0x17>;
    // else if (PSTATE.EL == EL3)
    //     PSTATE.UAO = (X<t,0x40>)<0x17>;
}


/**
 * ALLINT - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ALLINT(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fNmi)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xffffffffffffdfff)) | (uValue & 0x2000);
    else
        pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xffffffffffffdfff)) | (uValue & 0x2000);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_NMI))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && IsHCRXEL2Enabled() && AArch64.HCRX_EL2.TALLINT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         PSTATE.ALLINT = (X<t,0x40>)<0xd>;
    // else if (PSTATE.EL == EL2)
    //     PSTATE.ALLINT = (X<t,0x40>)<0xd>;
    // else if (PSTATE.EL == EL3)
    //     PSTATE.ALLINT = (X<t,0x40>)<0xd>;
}


/**
 * PM - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PM(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEbep)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xfffffffeffffffff)) | (uValue & UINT64_C(0x100000000));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_EBEP))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     PSTATE.PM = (X<t,0x40>)<0x20>;
    // else if (PSTATE.EL == EL2)
    //     PSTATE.PM = (X<t,0x40>)<0x20>;
    // else if (PSTATE.EL == EL3)
    //     PSTATE.PM = (X<t,0x40>)<0x20>;
}


/**
 * ICC_PMR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0100', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 5 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_PMR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (AArch64.ICC_SRE_EL1.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && AArch64.ICH_HCR_EL2.TC == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(3)/*FMO*/))
            ICV_PMR_EL1 = uValue;
        else if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(4)/*IMO*/))
            ICV_PMR_EL1 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,6,0),
                                         "ICC_PMR_EL1",
                                         uValue,
                                         uInstrEssence);
    }
    else
    {
        if (AArch64.ICC_SRE_EL2.SRE == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,6,0), "ICC_PMR_EL1", uValue, uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GICv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL1.SRE == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
    //         ICV_PMR_EL1 = X<t,0x40>;
    //     else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
    //         ICV_PMR_EL1 = X<t,0x40>;
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_PMR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         Undefined()
    //     else if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && (AArch64.SCR_EL3.IRQ):(AArch64.SCR_EL3.FIQ) == '11')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_PMR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_PMR_EL1 = X<t,0x40>;
}


/**
 * AFSR0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AFSR0_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x128, uValue);
        pVCpu->cpum.GstCtx.Afsr0.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,0),
                                         "AFSR0_EL2",
                                         uValue,
                                         uInstrEssence);
        pVCpu->cpum.GstCtx.Afsr0.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.AFSR0_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x128> = X<t,0x40>;
    //     else
    //         AFSR0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AFSR0_EL2 = X<t,0x40>;
    //     else
    //         AFSR0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     AFSR0_EL1 = X<t,0x40>;
}


/**
 * AFSR1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AFSR1_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x130, uValue);
        pVCpu->cpum.GstCtx.Afsr1.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,1),
                                         "AFSR1_EL2",
                                         uValue,
                                         uInstrEssence);
        pVCpu->cpum.GstCtx.Afsr1.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.AFSR1_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x130> = X<t,0x40>;
    //     else
    //         AFSR1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AFSR1_EL2 = X<t,0x40>;
    //     else
    //         AFSR1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     AFSR1_EL1 = X<t,0x40>;
}


/**
 * ESR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ESR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x138, uValue);
        pVCpu->cpum.GstCtx.Esr.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.EsrEl2.u64 = uValue;
        else
            pVCpu->cpum.GstCtx.Esr.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ESR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x138> = X<t,0x40>;
    //     else
    //         ESR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         ESR_EL2 = X<t,0x40>;
    //     else
    //         ESR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ESR_EL1 = X<t,0x40>;
}


/**
 * ERRSELR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ERRSELR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,1), "ERRSELR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,1), "ERRSELR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ERRSELR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERRSELR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERRSELR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ERRSELR_EL1 = X<t,0x40>;
}


/**
 * ERXCTLR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ERXCTLR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,1), "ERXCTLR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,1), "ERXCTLR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ERXCTLR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXCTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXCTLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ERXCTLR_EL1 = X<t,0x40>;
}


/**
 * ERXSTATUS_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ERXSTATUS_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,2),
                                     "ERXSTATUS_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,2), "ERXSTATUS_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ERXSTATUS_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXSTATUS_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXSTATUS_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ERXSTATUS_EL1 = X<t,0x40>;
}


/**
 * ERXADDR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ERXADDR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,3), "ERXADDR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,3), "ERXADDR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ERXADDR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXADDR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXADDR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ERXADDR_EL1 = X<t,0x40>;
}


/**
 * ERXPFGCTL_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ERXPFGCTL_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRasV1p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(47)/*FIEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,5),
                                     "ERXPFGCTL_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,5), "ERXPFGCTL_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RASv1p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIEN == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FIEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ERXPFGCTL_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIEN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXPFGCTL_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIEN == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIEN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXPFGCTL_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ERXPFGCTL_EL1 = X<t,0x40>;
}


/**
 * ERXPFGCDN_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0100', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ERXPFGCDN_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRasV1p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(47)/*FIEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,6),
                                     "ERXPFGCDN_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,6), "ERXPFGCDN_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RASv1p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIEN == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FIEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ERXPFGCDN_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIEN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXPFGCDN_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIEN == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FIEN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXPFGCDN_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ERXPFGCDN_EL1 = X<t,0x40>;
}


/**
 * ERXMISC0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ERXMISC0_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,0),
                                     "ERXMISC0_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,0), "ERXMISC0_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ERXMISCn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXMISC0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXMISC0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ERXMISC0_EL1 = X<t,0x40>;
}


/**
 * ERXMISC1_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ERXMISC1_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,1),
                                     "ERXMISC1_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,1), "ERXMISC1_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ERXMISCn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXMISC1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXMISC1_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ERXMISC1_EL1 = X<t,0x40>;
}


/**
 * ERXMISC2_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0101', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ERXMISC2_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRasV1p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,2),
                                     "ERXMISC2_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,2), "ERXMISC2_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RASv1p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ERXMISCn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXMISC2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXMISC2_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ERXMISC2_EL1 = X<t,0x40>;
}


/**
 * ERXMISC3_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ERXMISC3_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRasV1p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(36)/*TERR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,3),
                                     "ERXMISC3_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,3), "ERXMISC3_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RASv1p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TERR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.ERXMISCn_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXMISC3_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TWERR == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TWERR == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ERXMISC3_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ERXMISC3_EL1 = X<t,0x40>;
}


/**
 * TFSR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TFSR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 3)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(56)/*ATA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x190, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,0), "TFSR_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,6,0), "TFSR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,0), "TFSR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() == '011')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.ATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x190> = X<t,0x40>;
    //     else
    //         TFSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         TFSR_EL2 = X<t,0x40>;
    //     else
    //         TFSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TFSR_EL1 = X<t,0x40>;
}


/**
 * TFSRE0_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0101', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TFSRE0_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(56)/*ATA*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,1), "TFSRE0_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,1), "TFSRE0_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.ATA == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TFSRE0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TFSRE0_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TFSRE0_EL1 = X<t,0x40>;
}


/**
 * FAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0110', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_FAR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x220, uValue);
        pVCpu->cpum.GstCtx.Far.u64 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.FarEl2.u64 = uValue;
        else
            pVCpu->cpum.GstCtx.Far.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.FAR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x220> = X<t,0x40>;
    //     else
    //         FAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         FAR_EL2 = X<t,0x40>;
    //     else
    //         FAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     FAR_EL1 = X<t,0x40>;
}


/**
 * PFAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0110', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PFAR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPfar)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x2d0, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,6,0,5), "PFAR_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,6,0,5), "PFAR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,6,0,5), "PFAR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PFAR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PFAREn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nPFAR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PFAREn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x2d0> = X<t,0x40>;
    //     else
    //         PFAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PFAREn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PFAREn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         PFAR_EL2 = X<t,0x40>;
    //     else
    //         PFAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PFAR_EL1 = X<t,0x40>;
}


/**
 * PAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0111', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PAR_EL1(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        pVCpu->cpum.GstCtx.Par.u64 = uValue;
    else
        pVCpu->cpum.GstCtx.Par.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGWTR_EL2.PAR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         PAR_EL1<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     PAR_EL1<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PAR_EL1<[0x3f:0]> = X<t,0x40>;
}


/**
 * PMBLIMITR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMBLIMITR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 12) & UINT32_C(0x3)/*E2PB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x800, uValue);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,0),
                                     "PMBLIMITR_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,0), "PMBLIMITR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMBLIMITR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2PB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x800> = X<t,0x40>;
    //     else
    //         PMBLIMITR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMBLIMITR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMBLIMITR_EL1 = X<t,0x40>;
}


/**
 * PMBPTR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMBPTR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 12) & UINT32_C(0x3)/*E2PB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x810, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,1), "PMBPTR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,1), "PMBPTR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMBPTR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2PB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x810> = X<t,0x40>;
    //     else
    //         PMBPTR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMBPTR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMBPTR_EL1 = X<t,0x40>;
}


/**
 * PMBSR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1010', 'op2': '011'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMBSR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 12) & UINT32_C(0x3)/*E2PB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x820, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,3), "PMBSR_EL1", uValue, uInstrEssence);
    }
    if (   EffectivePMSCR_EL2_EE() != 0
        && pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,10,3), "PMBSR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,3), "PMBSR_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMBSR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2PB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   EffectiveHCR_EL2_NVx() IN ('1x1')
    //              && (EffectivePMSCR_EL2_EE() == '00' || AArch64.PMSCR_EL1.EE == '00' || EffectiveHCR_EL2_NVx() == '111'))
    //         NVMem<0x820> = X<t,0x40>;
    //     else
    //         PMBSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectivePMSCR_EL2_EE() != '00' && ELIsInHost(EL2))
    //         PMBSR_EL2 = X<t,0x40>;
    //     else
    //         PMBSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMBSR_EL1 = X<t,0x40>;
}


/**
 * PMSDSFR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSDSFR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpeFds)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x858, uValue);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,4),
                                     "PMSDSFR_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,4), "PMSDSFR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE_FDS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMS3 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMSDSFR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMS3 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x858> = X<t,0x40>;
    //     else
    //         PMSDSFR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMS3 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMS3 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSDSFR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSDSFR_EL1 = X<t,0x40>;
}


/**
 * PMBMAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMBMAR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpeNvm)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 12) & UINT32_C(0x3)/*E2PB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,5), "PMBMAR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,5), "PMBMAR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE_nVM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMS4 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMBMAR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2PB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMS4 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMBMAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMS4 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMS4 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMBMAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMBMAR_EL1 = X<t,0x40>;
}


/**
 * TRBLIMITR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRBLIMITR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,0),
                                     "TRBLIMITR_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,0), "TRBLIMITR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRBLIMITR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBLIMITR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBLIMITR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBLIMITR_EL1 = X<t,0x40>;
}


/**
 * TRBPTR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRBPTR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,1), "TRBPTR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,1), "TRBPTR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRBPTR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBPTR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBPTR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBPTR_EL1 = X<t,0x40>;
}


/**
 * TRBBASER_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRBBASER_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,2),
                                     "TRBBASER_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,2), "TRBBASER_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRBBASER_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBBASER_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBBASER_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBBASER_EL1 = X<t,0x40>;
}


/**
 * TRBSR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '011'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRBSR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7 && EffectiveTRFCR_EL2_EE() != 0 && AArch64.TRFCR_EL1.EE != 0)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x860, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,3), "TRBSR_EL1", uValue, uInstrEssence);
    }
    if (   EffectiveTRFCR_EL2_EE() != 0
        && pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,11,3), "TRBSR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,3), "TRBSR_EL1", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRBSR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111') && EffectiveTRFCR_EL2_EE() != '00' && AArch64.TRFCR_EL1.EE != '00')
    //         NVMem<0x860> = X<t,0x40>;
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else if (EffectiveTRFCR_EL2_EE() != '00' && ELIsInHost(EL2))
    //         TRBSR_EL2 = X<t,0x40>;
    //     else
    //         TRBSR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBSR_EL1 = X<t,0x40>;
}


/**
 * TRBMAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRBMAR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,4), "TRBMAR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,4), "TRBMAR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRBMAR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBMAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBMAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBMAR_EL1 = X<t,0x40>;
}


/**
 * TRBMPAM_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRBMPAM_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbeMpam)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,5),
                                     "TRBMPAM_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,5), "TRBMPAM_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnTB2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && EL3SDDUndefPriority()
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nTRBMPAM_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnTB2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBMPAM_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnTB2 == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnTB2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBMPAM_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBMPAM_EL1 = X<t,0x40>;
}


/**
 * TRBTRG_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1011', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRBTRG_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (((pVCpu->cpum.GstCtx.MdcrEl2.u64 >> 24) & UINT32_C(0x3)/*E2TB*/) & 1) == 0)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,6), "TRBTRG_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,6), "TRBTRG_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.TRBTRG_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.E2TB IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBTRG_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBTRG_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
    //         Halt(DebugHalt_SoftwareAccess)
    //     else
    //         TRBTRG_EL1 = X<t,0x40>;
}


/**
 * PMSSCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSSCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3Ss)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,13,3), "PMSSCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3_SS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSS == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMSSCR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSSCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSSCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSSCR_EL1 = X<t,0x40>;
}


/**
 * PMINTENSET_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMINTENSET_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,1),
                                     "PMINTENSET_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,1), "PMINTENSET_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMINTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMINTENSET_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMINTENSET_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMINTENSET_EL1 = X<t,0x40>;
}


/**
 * PMINTENCLR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMINTENCLR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,2),
                                     "PMINTENCLR_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,2), "PMINTENCLR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMINTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMINTENCLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMINTENCLR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMINTENCLR_EL1 = X<t,0x40>;
}


/**
 * PMUACR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMUACR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3p9)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,4), "PMUACR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,4), "PMUACR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3p9))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMUACR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMUACR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMUACR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMUACR_EL1 = X<t,0x40>;
}


/**
 * PMECR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMECR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEbep && !pGstFeats->fPmuV3Ss)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,5), "PMECR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,5), "PMECR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_EBEP) || IsFeatureImplemented(FEAT_PMUv3_SS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMECR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMECR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMECR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMECR_EL1 = X<t,0x40>;
}


/**
 * PMIAR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMIAR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSebep)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,7), "PMIAR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,7), "PMIAR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SEBEP))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMIAR_EL1 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMIAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMIAR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMIAR_EL1 = X<t,0x40>;
}


/**
 * PMSCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x828, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,0), "PMSCR_EL1", uValue, uInstrEssence);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,9,0), "PMSCR_EL2", uValue, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,0), "PMSCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMSCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x828> = X<t,0x40>;
    //     else
    //         PMSCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (ELIsInHost(EL2))
    //         PMSCR_EL2 = X<t,0x40>;
    //     else
    //         PMSCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSCR_EL1 = X<t,0x40>;
}


/**
 * PMSNEVFR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSNEVFR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpeFnE)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x850, uValue);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,1),
                                     "PMSNEVFR_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,1), "PMSNEVFR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE_FnE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSN == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.nPMSNEVFR_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x850> = X<t,0x40>;
    //     else
    //         PMSNEVFR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPMSN == '0')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPMSN == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSNEVFR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSNEVFR_EL1 = X<t,0x40>;
}


/**
 * PMSICR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSICR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x838, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,2), "PMSICR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,2), "PMSICR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMSICR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x838> = X<t,0x40>;
    //     else
    //         PMSICR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSICR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSICR_EL1 = X<t,0x40>;
}


/**
 * PMSIRR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSIRR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x840, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,3), "PMSIRR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,3), "PMSIRR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMSIRR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x840> = X<t,0x40>;
    //     else
    //         PMSIRR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSIRR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSIRR_EL1 = X<t,0x40>;
}


/**
 * PMSFCR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSFCR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,4), "PMSFCR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,4), "PMSFCR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMSFCR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSFCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSFCR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSFCR_EL1 = X<t,0x40>;
}


/**
 * PMSEVFR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSEVFR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x830, uValue);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,5), "PMSEVFR_EL1", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,5), "PMSEVFR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMSEVFR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x830> = X<t,0x40>;
    //     else
    //         PMSEVFR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSEVFR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSEVFR_EL1 = X<t,0x40>;
}


/**
 * PMSLATFR_EL1 - OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1001', 'CRm': '1001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSLATFR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(14)/*TPMS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x848, uValue);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,6),
                                     "PMSLATFR_EL1",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,6), "PMSLATFR_EL1", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMSLATFR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x848> = X<t,0x40>;
    //     else
    //         PMSLATFR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSLATFR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSLATFR_EL1 = X<t,0x40>;
}


/**
 * CSSELR_EL1 - OrderedDict({'op0': '11', 'op1': '010', 'CRn': '0000', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CSSELR_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(17)/*TID2*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fEvt && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(49)/*TID4*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        pVCpu->cpum.GstCtx.Csselr.u64 = uValue;
    }
    else
        pVCpu->cpum.GstCtx.Csselr.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TID2 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && IsFeatureImplemented(FEAT_EVT) && AArch64.HCR_EL2.TID4 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.CSSELR_EL1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         CSSELR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     CSSELR_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CSSELR_EL1 = X<t,0x40>;
}


/**
 * POR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1010', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_POR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Poe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Cpacr.u64 & RT_BIT_32(29)/*E0POE*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(29)/*E0POE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,10,2,4), "POR_EL0", uValue, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(26)/*TVM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,10,2,4), "POR_EL0", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,10,2,4), "POR_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.CPACR_EL1.E0POE == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nPOR_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CPTR_EL2.E0POE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         POR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nPOR_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         POR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         POR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     POR_EL0 = X<t,0x40>;
}


/**
 * TPIDR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TPIDR_EL0(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        pVCpu->cpum.GstCtx.aTpIdr[0].u64 = uValue;
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        pVCpu->cpum.GstCtx.aTpIdr[0].u64 = uValue;
    else
        pVCpu->cpum.GstCtx.aTpIdr[0].u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (   EL2Enabled()
    //         && !ELIsInHost(EL0)
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGWTR_EL2.TPIDR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         TPIDR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGWTR_EL2.TPIDR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         TPIDR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     TPIDR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TPIDR_EL0 = X<t,0x40>;
}


/**
 * TPIDRRO_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TPIDRRO_EL0(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        pVCpu->cpum.GstCtx.TpIdrRoEl0.u64 = uValue;
    else
        pVCpu->cpum.GstCtx.TpIdrRoEl0.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   EL2Enabled()
    //         && IsFeatureImplemented(FEAT_FGT)
    //         && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //         && AArch64.HFGWTR_EL2.TPIDRRO_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         TPIDRRO_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     TPIDRRO_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TPIDRRO_EL0 = X<t,0x40>;
}


/**
 * TPIDR2_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TPIDR2_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_64(60)/*EnTP2*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_64(60)/*EnTP2*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,5), "TPIDR2_EL0", uValue, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,5), "TPIDR2_EL0", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,5), "TPIDR2_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnTP2 == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.EnTP2 == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.EnTP2 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nTPIDR2_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnTP2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TPIDR2_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnTP2 == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nTPIDR2_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnTP2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TPIDR2_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnTP2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnTP2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TPIDR2_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TPIDR2_EL0 = X<t,0x40>;
}


/**
 * SCXTNUM_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCXTNUM_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fCvs2_2 && !pGstFeats->fCsv21p2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(20)/*TSCXT*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(53)/*EnSCXT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && (pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(20)/*TSCXT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,7),
                                     "SCXTNUM_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(53)/*EnSCXT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,7),
                                     "SCXTNUM_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,7), "SCXTNUM_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_CSV2_2) || IsFeatureImplemented(FEAT_CSV2_1p2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.TSCXT == '1')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.EnSCXT == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.SCXTNUM_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.TSCXT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SCXTNUM_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.HCR_EL2.EnSCXT == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.SCXTNUM_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SCXTNUM_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SCXTNUM_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCXTNUM_EL0 = X<t,0x40>;
}


/**
 * AMCR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMCR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (   (pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 2)
        || (!pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,0), "AMCR_EL0", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (IsHighestEL(PSTATE.EL))
    //     AMCR_EL0 = X<t,0x40>;
    // else
    //     Undefined()
}


/**
 * AMUSERENR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMUSERENR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(30)/*TAM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,3),
                                     "AMUSERENR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,3), "AMUSERENR_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (EL2Enabled() && AArch64.CPTR_EL2.TAM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         AMUSERENR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         AMUSERENR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     AMUSERENR_EL0 = X<t,0x40>;
}


/**
 * AMCNTENCLR0_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMCNTENCLR0_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (   (pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 2)
        || (!pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,4),
                                     "AMCNTENCLR0_EL0",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (IsHighestEL(PSTATE.EL))
    //     AMCNTENCLR0_EL0 = X<t,0x40>;
    // else
    //     Undefined()
}


/**
 * AMCNTENSET0_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMCNTENSET0_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (   (pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 2)
        || (!pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,5),
                                     "AMCNTENSET0_EL0",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (IsHighestEL(PSTATE.EL))
    //     AMCNTENSET0_EL0 = X<t,0x40>;
    // else
    //     Undefined()
}


/**
 * AMCNTENCLR1_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMCNTENCLR1_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (   (pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 2)
        || (!pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,3,0),
                                     "AMCNTENCLR1_EL0",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (IsHighestEL(PSTATE.EL))
    //     AMCNTENCLR1_EL0 = X<t,0x40>;
    // else
    //     Undefined()
}


/**
 * AMCNTENSET1_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMCNTENSET1_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1)
        return iemRaiseUndefined(pVCpu);
    if (   (pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 2)
        || (!pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,3,1),
                                     "AMCNTENSET1_EL0",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AMUv1))
    //     Undefined()
    // else if (IsHighestEL(PSTATE.EL))
    //     AMCNTENSET1_EL0 = X<t,0x40>;
    // else
    //     Undefined()
}


/**
 * CNTFRQ_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTFRQ_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (   (pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 2)
        || (!pGstFeats->fEl2 && IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,0,0), "CNTFRQ_EL0", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (IsHighestEL(PSTATE.EL))
    //     CNTFRQ_EL0 = X<t,0x40>;
    // else
    //     Undefined()
}


/**
 * PMCCFILTR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '1111', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMCCFILTR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fPmuV3p9
            && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)
            && (   !(iemCImplHlpGetPmUacrEl1(pVCpu) & RT_BIT_32(31)/*C*/)
                || (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(2)/*CR*/)))
            return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7),
                                     "PMCCFILTR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7),
                                     "PMCCFILTR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7), "PMCCFILTR_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMCCFILTR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_PMUv3p9)
    //              && PMUSERENR_EL0.UEN == '1'
    //              && (AArch64.PMUACR_EL1.C == '0' || AArch64.PMUSERENR_EL0.CR == '1'))
    //         return;
    //     else
    //         PMCCFILTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMCCFILTR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCCFILTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCCFILTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMCCFILTR_EL0 = X<t,0x40>;
}


/**
 * CNTP_TVAL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTP_TVAL_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(9)/*EL0PTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(9)/*EL0PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            pVCpu->cpum.GstCtx.CntHpCValEl2.u64 = (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                         "CNTP_CVAL_EL0",
                                         (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu),
                                         uInstrEssence);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                     "CNTP_CVAL_EL0",
                                     (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu),
                                     uInstrEssence);
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.CntHpCValEl2.u64 = (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                         "CNTP_CVAL_EL0",
                                         (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu),
                                         uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0PTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.HCR_EL2.TGE == '0' && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHPS_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHP_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    //     else if (   IsFeatureImplemented(FEAT_ECV_POFF)
    //              && EL2Enabled()
    //              && SCR_EL3.ECVEn == '1'
    //              && CNTHCTL_EL2.ECV == '1'
    //              && !ELIsInHost(EL0))
    //         CNTP_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt() - CNTPOFF_EL2;
    //     else
    //         CNTP_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_ECV_POFF)
    //              && EL2Enabled()
    //              && AArch64.SCR_EL3.ECVEn == '1'
    //              && AArch64.CNTHCTL_EL2.ECV == '1')
    //         CNTP_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt() - CNTPOFF_EL2;
    //     else
    //         CNTP_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHPS_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHP_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    //     else
    //         CNTP_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    // else if (PSTATE.EL == EL3)
    //     CNTP_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
}


/**
 * CNTP_CTL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTP_CTL_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(9)/*EL0PTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(9)/*EL0PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            pVCpu->cpum.GstCtx.CntHpCtlEl2.u64 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,1),
                                         "CNTP_CTL_EL0",
                                         uValue,
                                         uInstrEssence);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x180, uValue);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,1),
                                     "CNTP_CTL_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.CntHpCtlEl2.u64 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,1),
                                         "CNTP_CTL_EL0",
                                         uValue,
                                         uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0PTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.HCR_EL2.TGE == '0' && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHPS_CTL_EL2 = X<t,0x40>;
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHP_CTL_EL2 = X<t,0x40>;
    //     else
    //         CNTP_CTL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x180> = X<t,0x40>;
    //     else
    //         CNTP_CTL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHPS_CTL_EL2 = X<t,0x40>;
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHP_CTL_EL2 = X<t,0x40>;
    //     else
    //         CNTP_CTL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTP_CTL_EL0 = X<t,0x40>;
}


/**
 * CNTP_CVAL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTP_CVAL_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(9)/*EL0PTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(9)/*EL0PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            pVCpu->cpum.GstCtx.CntHpCValEl2.u64 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                         "CNTP_CVAL_EL0",
                                         uValue,
                                         uInstrEssence);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(1)/*EL1PCEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(11)/*EL1PTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x178, uValue);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                     "CNTP_CVAL_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.CntHpCValEl2.u64 = uValue;
        else
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                         "CNTP_CVAL_EL0",
                                         uValue,
                                         uInstrEssence);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0PTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.HCR_EL2.TGE == '0' && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHPS_CVAL_EL2 = X<t,0x40>;
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHP_CVAL_EL2 = X<t,0x40>;
    //     else
    //         CNTP_CVAL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PCEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL2) && AArch64.CNTHCTL_EL2.EL1PTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x178> = X<t,0x40>;
    //     else
    //         CNTP_CVAL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHPS_CVAL_EL2 = X<t,0x40>;
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHP_CVAL_EL2 = X<t,0x40>;
    //     else
    //         CNTP_CVAL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTP_CVAL_EL0 = X<t,0x40>;
}


/**
 * CNTV_TVAL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTV_TVAL_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(8)/*EL0VTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(8)/*EL0VTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && pGstFeats->fEcv
            && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,2),
                                         "CNTHV_CVAL_EL2",
                                         (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu),
                                         uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)))
            pVCpu->cpum.GstCtx.CntvCValEl0 = (  (int64_t)(int32_t)(uValue)
                                              + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu)
                                              - pVCpu->cpum.GstCtx.CntVOffEl2.u64 );
        else
            pVCpu->cpum.GstCtx.CntvCValEl0 = (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fEcv && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2)
            pVCpu->cpum.GstCtx.CntvCValEl0 = (  (int64_t)(int32_t)(uValue)
                                              + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu)
                                              - pVCpu->cpum.GstCtx.CntVOffEl2.u64 );
        else
            pVCpu->cpum.GstCtx.CntvCValEl0 = (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,2),
                                         "CNTHV_CVAL_EL2",
                                         (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu),
                                         uInstrEssence);
        if (   !pGstFeats->fVhe
            || !pGstFeats->fEl2
            || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            pVCpu->cpum.GstCtx.CntvCValEl0 = (  (int64_t)(int32_t)(uValue)
                                              + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu)
                                              - pVCpu->cpum.GstCtx.CntVOffEl2.u64 );
        else
            pVCpu->cpum.GstCtx.CntvCValEl0 = (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0VTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0VTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHVS_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHV_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    //     else if (HaveEL(EL2) && !ELIsInHost(EL0))
    //         CNTV_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt() - CNTVOFF_EL2;
    //     else
    //         CNTV_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL2))
    //         CNTV_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt() - CNTVOFF_EL2;
    //     else
    //         CNTV_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHVS_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHV_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    //     else if (!ELIsInHost(EL2))
    //         CNTV_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt() - CNTVOFF_EL2;
    //     else
    //         CNTV_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    // else if (PSTATE.EL == EL3)
    //     if (HaveEL(EL2) && !ELUsingAArch32(EL2))
    //         CNTV_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt() - CNTVOFF_EL2;
    //     else if (HaveEL(EL2) && ELUsingAArch32(EL2))
    //         CNTV_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt() - CNTVOFF;
    //     else
    //         CNTV_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
}


/**
 * CNTV_CTL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTV_CTL_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(8)/*EL0VTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(8)/*EL0VTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && pGstFeats->fEcv
            && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,1),
                                         "CNTHV_CTL_EL2",
                                         uValue,
                                         uInstrEssence);
        pVCpu->cpum.GstCtx.CntvCtlEl0 = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fEcv && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x170, uValue);
        pVCpu->cpum.GstCtx.CntvCtlEl0 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,1),
                                         "CNTHV_CTL_EL2",
                                         uValue,
                                         uInstrEssence);
        pVCpu->cpum.GstCtx.CntvCtlEl0 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0VTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0VTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHVS_CTL_EL2 = X<t,0x40>;
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHV_CTL_EL2 = X<t,0x40>;
    //     else
    //         CNTV_CTL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x170> = X<t,0x40>;
    //     else
    //         CNTV_CTL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHVS_CTL_EL2 = X<t,0x40>;
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHV_CTL_EL2 = X<t,0x40>;
    //     else
    //         CNTV_CTL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTV_CTL_EL0 = X<t,0x40>;
}


/**
 * CNTV_CVAL_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTV_CVAL_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.CntKCtl.u64 & RT_BIT_32(8)/*EL0VTEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(8)/*EL0VTEN*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && pGstFeats->fEcv
            && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,2),
                                         "CNTHV_CVAL_EL2",
                                         uValue,
                                         uInstrEssence);
        pVCpu->cpum.GstCtx.CntvCValEl0 = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fEcv && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(13)/*EL1TVT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 7)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x168, uValue);
        pVCpu->cpum.GstCtx.CntvCValEl0 = uValue;
    }
    else
    {
        if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,2),
                                         "CNTHV_CVAL_EL2",
                                         uValue,
                                         uInstrEssence);
        pVCpu->cpum.GstCtx.CntvCValEl0 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.CNTKCTL_EL1.EL0VTEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL0VTEN == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHVS_CVAL_EL2 = X<t,0x40>;
    //     else if (ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHV_CVAL_EL2 = X<t,0x40>;
    //     else
    //         CNTV_CVAL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && IsFeatureImplemented(FEAT_ECV) && AArch64.CNTHCTL_EL2.EL1TVT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EffectiveHCR_EL2_NVx() IN ('111'))
    //         NVMem<0x168> = X<t,0x40>;
    //     else
    //         CNTV_CVAL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2))
    //         CNTHVS_CVAL_EL2 = X<t,0x40>;
    //     else if (ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure))
    //         CNTHV_CVAL_EL2 = X<t,0x40>;
    //     else
    //         CNTV_CVAL_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTV_CVAL_EL0 = X<t,0x40>;
}


/**
 * GCSPR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GCSPR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,2,5,1), "GCSPR_EL0", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,2,5,1), "GCSPR_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGWTR_EL2.nGCS_EL0 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GCSPR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GCSPR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     GCSPR_EL0 = X<t,0x40>;
}


/**
 * NZCV - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_NZCV(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xffffffff0fffffff)) | (uValue & UINT32_C(0xf0000000));
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     (PSTATE.N):(PSTATE.Z):(PSTATE.C):(PSTATE.V) = (X<t,0x40>)<[0x1f:0x1c]>;
    // else if (PSTATE.EL == EL1)
    //     (PSTATE.N):(PSTATE.Z):(PSTATE.C):(PSTATE.V) = (X<t,0x40>)<[0x1f:0x1c]>;
    // else if (PSTATE.EL == EL2)
    //     (PSTATE.N):(PSTATE.Z):(PSTATE.C):(PSTATE.V) = (X<t,0x40>)<[0x1f:0x1c]>;
    // else if (PSTATE.EL == EL3)
    //     (PSTATE.N):(PSTATE.Z):(PSTATE.C):(PSTATE.V) = (X<t,0x40>)<[0x1f:0x1c]>;
}


/**
 * DAIF - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_DAIF(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   pGstFeats->fVhe
                && pGstFeats->fEl2
                && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            || !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(9)/*UMA*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xfffffffffffffc3f)) | (uValue & 0x3c0);
    }
    else
        pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xfffffffffffffc3f)) | (uValue & 0x3c0);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (ELIsInHost(EL0) || AArch64.SCTLR_EL1.UMA == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else
    //         (PSTATE.D):(PSTATE.A):(PSTATE.I):(PSTATE.F) = (X<t,0x40>)<[9:6]>;
    // else if (PSTATE.EL == EL1)
    //     (PSTATE.D):(PSTATE.A):(PSTATE.I):(PSTATE.F) = (X<t,0x40>)<[9:6]>;
    // else if (PSTATE.EL == EL2)
    //     (PSTATE.D):(PSTATE.A):(PSTATE.I):(PSTATE.F) = (X<t,0x40>)<[9:6]>;
    // else if (PSTATE.EL == EL3)
    //     (PSTATE.D):(PSTATE.A):(PSTATE.I):(PSTATE.F) = (X<t,0x40>)<[9:6]>;
}


/**
 * SVCR - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SVCR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && ((pVCpu->cpum.GstCtx.Cpacr.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrapSme(pVCpu, 2);
            return iemRaiseSystemAccessTrapSme(pVCpu, 1);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && ((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) != 3)
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,2), "SVCR", uValue, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,2), "SVCR", uValue, uInstrEssence);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,2), "SVCR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.CPACR_EL1.SMEN != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x1d)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x1d)
    //     else if (ELIsInHost(EL0) && AArch64.CPTR_EL2.SMEN != '11')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         SVCR = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 0x1d)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         SVCR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         SVCR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         SVCR = X<t,0x40>;
}


/**
 * DIT - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_DIT(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fDit)
        return iemRaiseUndefined(pVCpu);
    pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xfffffffffeffffff)) | (uValue & 0x1000000);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_DIT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     PSTATE.DIT = (X<t,0x40>)<0x18>;
    // else if (PSTATE.EL == EL1)
    //     PSTATE.DIT = (X<t,0x40>)<0x18>;
    // else if (PSTATE.EL == EL2)
    //     PSTATE.DIT = (X<t,0x40>)<0x18>;
    // else if (PSTATE.EL == EL3)
    //     PSTATE.DIT = (X<t,0x40>)<0x18>;
}


/**
 * SSBS - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SSBS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSsbs2)
        return iemRaiseUndefined(pVCpu);
    pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xffffffffffffefff)) | (uValue & 0x1000);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SSBS2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     PSTATE.SSBS = (X<t,0x40>)<0xc>;
    // else if (PSTATE.EL == EL1)
    //     PSTATE.SSBS = (X<t,0x40>)<0xc>;
    // else if (PSTATE.EL == EL2)
    //     PSTATE.SSBS = (X<t,0x40>)<0xc>;
    // else if (PSTATE.EL == EL3)
    //     PSTATE.SSBS = (X<t,0x40>)<0xc>;
}


/**
 * TCO - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0010', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCO(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    pVCpu->cpum.GstCtx.fPState = (pVCpu->cpum.GstCtx.fPState & UINT64_C(0xfffffffffdffffff)) | (uValue & 0x2000000);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     PSTATE.TCO = (X<t,0x40>)<0x19>;
    // else if (PSTATE.EL == EL1)
    //     PSTATE.TCO = (X<t,0x40>)<0x19>;
    // else if (PSTATE.EL == EL2)
    //     PSTATE.TCO = (X<t,0x40>)<0x19>;
    // else if (PSTATE.EL == EL3)
    //     PSTATE.TCO = (X<t,0x40>)<0x19>;
}


/**
 * FPCR - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_FPCR(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && ((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrapUnknown(pVCpu, 2);
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && ((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        pVCpu->cpum.GstCtx.fpcr = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        pVCpu->cpum.GstCtx.fpcr = uValue;
    }
    else
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        pVCpu->cpum.GstCtx.fpcr = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.CPACR_EL1.FPEN != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 7)
    //     else if (ELIsInHost(EL0) && AArch64.CPTR_EL2.FPEN != '11')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPCR = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPCR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPCR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TFP == '1')
    //         AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPCR = X<t,0x40>;
}


/**
 * FPSR - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_FPSR(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && ((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrapUnknown(pVCpu, 2);
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && ((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        pVCpu->cpum.GstCtx.fpsr = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        pVCpu->cpum.GstCtx.fpsr = uValue;
    }
    else
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        pVCpu->cpum.GstCtx.fpsr = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.CPACR_EL1.FPEN != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 7)
    //     else if (ELIsInHost(EL0) && AArch64.CPTR_EL2.FPEN != '11')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPSR = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (AArch64.CPACR_EL1.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPSR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPSR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TFP == '1')
    //         AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPSR = X<t,0x40>;
}


/**
 * FPMR - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_FPMR(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFpmr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_64(34)/*EnFPM*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_64(34)/*EnFPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && ((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrapUnknown(pVCpu, 2);
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && ((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) != 3)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,2), "FPMR", uValue, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if ((((pVCpu->cpum.GstCtx.Cpacr.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 1);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
            && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,2), "FPMR", uValue, uInstrEssence);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
        return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,2), "FPMR", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FPMR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnFPM == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.EnFPM == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.EnFPM == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && AArch64.SCR_EL3.HXEn == '0') || AArch64.HCRX_EL2.EnFPM == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnFPM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!ELIsInHost(EL0) && AArch64.CPACR_EL1.FPEN != '11')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 7)
    //     else if (ELIsInHost(EL0) && AArch64.CPTR_EL2.FPEN != '11')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPMR = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnFPM == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && AArch64.SCR_EL3.HXEn == '0') || AArch64.HCRX_EL2.EnFPM == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnFPM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (AArch64.CPACR_EL1.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL1, 7)
    //     else if (EL2Enabled() && !ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPMR = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnFPM == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnFPM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPMR = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TFP == '1')
    //         AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPMR = X<t,0x40>;
}


/**
 * DSPSR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_DSPSR_EL0(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!Halted())
    //     Undefined()
    // else
    //     DSPSR_EL0 = X<t,0x40>;
}


/**
 * DLR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '0100', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_DLR_EL0(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!Halted())
    //     Undefined()
    // else
    //     DLR_EL0 = X<t,0x40>;
}


/**
 * PMCR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMCR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            || (pGstFeats->fPmuV3p9 && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(5)/*TPMCR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,0), "PMCR_EL0", uValue, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(5)/*TPMCR*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,0), "PMCR_EL0", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,0), "PMCR_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' || (IsFeatureImplemented(FEAT_PMUv3p9) && AArch64.PMUSERENR_EL0.UEN == '1'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMCR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMCR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMCR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPMCR == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMCR_EL0 = X<t,0x40>;
}


/**
 * PMCNTENSET_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMCNTENSET_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,1),
                                     "PMCNTENSET_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,1),
                                     "PMCNTENSET_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,1), "PMCNTENSET_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMCNTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCNTENSET_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMCNTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCNTENSET_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCNTENSET_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMCNTENSET_EL0 = X<t,0x40>;
}


/**
 * PMCNTENCLR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMCNTENCLR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,2),
                                     "PMCNTENCLR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,2),
                                     "PMCNTENCLR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,2), "PMCNTENCLR_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMCNTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCNTENCLR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMCNTEN == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCNTENCLR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCNTENCLR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMCNTENCLR_EL0 = X<t,0x40>;
}


/**
 * PMOVSCLR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMOVSCLR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,3),
                                     "PMOVSCLR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,3),
                                     "PMOVSCLR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,3), "PMOVSCLR_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMOVS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMOVSCLR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMOVS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMOVSCLR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMOVSCLR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMOVSCLR_EL0 = X<t,0x40>;
}


/**
 * PMSWINC_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSWINC_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (pGstFeats->fPmuV3p9 && !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT64_C(0x13) /*UEN,SW,EN*/))
            || (!pGstFeats->fPmuV3p9 && !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT64_C(0x3) /*SW,EN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,4),
                                     "PMSWINC_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,4),
                                     "PMSWINC_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,4), "PMSWINC_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   (   IsFeatureImplemented(FEAT_PMUv3p9)
    //                  && (AArch64.PMUSERENR_EL0.UEN):(AArch64.PMUSERENR_EL0.SW):(AArch64.PMUSERENR_EL0.EN) == '000')
    //              || (!IsFeatureImplemented(FEAT_PMUv3p9) && (AArch64.PMUSERENR_EL0.SW):(AArch64.PMUSERENR_EL0.EN) == '00'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMSWINC_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSWINC_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMSWINC_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSWINC_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSWINC_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSWINC_EL0 = X<t,0x40>;
}


/**
 * PMSELR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSELR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (pGstFeats->fPmuV3p9 && !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT64_C(0x19) /*UEN,ER,EN*/))
            || (!pGstFeats->fPmuV3p9 && !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT64_C(0x9) /*ER,EN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,5), "PMSELR_EL0", uValue, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,5), "PMSELR_EL0", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,5), "PMSELR_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   (   IsFeatureImplemented(FEAT_PMUv3p9)
    //                  && (AArch64.PMUSERENR_EL0.UEN):(AArch64.PMUSERENR_EL0.ER):(AArch64.PMUSERENR_EL0.EN) == '000')
    //              || (!IsFeatureImplemented(FEAT_PMUv3p9) && (AArch64.PMUSERENR_EL0.ER):(AArch64.PMUSERENR_EL0.EN) == '00'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMSELR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSELR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMSELR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSELR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSELR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSELR_EL0 = X<t,0x40>;
}


/**
 * PMCCNTR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMCCNTR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fPmuV3p9
            && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)
            && (   !(iemCImplHlpGetPmUacrEl1(pVCpu) & RT_BIT_32(31)/*C*/)
                || (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(2)/*CR*/)))
            return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,0),
                                     "PMCCNTR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,0),
                                     "PMCCNTR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,0), "PMCCNTR_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMCCNTR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_PMUv3p9)
    //              && PMUSERENR_EL0.UEN == '1'
    //              && (AArch64.PMUACR_EL1.C == '0' || AArch64.PMUSERENR_EL0.CR == '1'))
    //         return;
    //     else
    //         PMCCNTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMCCNTR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCCNTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMCCNTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMCCNTR_EL0 = X<t,0x40>;
}


/**
 * PMXEVTYPER_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1101', 'op2': '001'})
 * Transformation status: 47 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMXEVTYPER_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (UInt(AArch64.PMSELR_EL0.SEL) != 0x1f && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersSelfHosted())
    {
        if (pGstFeats->fFgt)
            return iemRaiseUndefined(pVCpu);
        ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && UInt(AArch64.PMSELR_EL0.SEL) != 0x1f
            && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
        {
            if (!pGstFeats->fFgt)
                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
            else
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        }
        else if (   pGstFeats->fPmuV3p9
                 && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)
                 && (   (   UInt(AArch64.PMSELR_EL0.SEL) != 0x1f
                         && (   (AArch64.PMUACR_EL1)<UInt(AArch64.PMSELR_EL0.SEL)> == 0
                             || (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(3)/*ER*/)))
                     || (   UInt(AArch64.PMSELR_EL0.SEL) == 0x1f
                         && (   !(iemCImplHlpGetPmUacrEl1(pVCpu) & RT_BIT_32(31)/*C*/)
                             || (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(2)/*CR*/)))))
            return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
        else if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7),
                                         "PMCCFILTR_EL0",
                                         uValue,
                                         uInstrEssence);
        else
            PMEVTYPER_EL0<UInt(AArch64.PMSELR_EL0.SEL)> = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && UInt(AArch64.PMSELR_EL0.SEL) != 0x1f
            && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
        {
            if (!pGstFeats->fFgt)
                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
            else
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        }
        else if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7),
                                         "PMCCFILTR_EL0",
                                         uValue,
                                         uInstrEssence);
        else
            PMEVTYPER_EL0<UInt(AArch64.PMSELR_EL0.SEL)> = uValue;
    }
    else
    {
        if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7),
                                         "PMCCFILTR_EL0",
                                         uValue,
                                         uInstrEssence);
        PMEVTYPER_EL0<UInt(AArch64.PMSELR_EL0.SEL)> = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (UInt(AArch64.PMSELR_EL0.SEL) != 0x1f && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersSelfHosted())
    //     if (IsFeatureImplemented(FEAT_FGT))
    //         Undefined()
    //     else
    //         ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMEVTYPERn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && UInt(AArch64.PMSELR_EL0.SEL) != 0x1f
    //              && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
    //         if (!IsFeatureImplemented(FEAT_FGT))
    //             ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_PMUv3p9)
    //              && PMUSERENR_EL0.UEN == '1'
    //              && (   (   UInt(AArch64.PMSELR_EL0.SEL) != 0x1f
    //                      && ((AArch64.PMUACR_EL1)<UInt(AArch64.PMSELR_EL0.SEL)> == '0' || AArch64.PMUSERENR_EL0.ER == '1'))
    //                  || (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f && (AArch64.PMUACR_EL1.C == '0' || AArch64.PMUSERENR_EL0.CR == '1'))))
    //         return;
    //     else if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
    //         PMCCFILTR_EL0 = X<t,0x40>;
    //     else
    //         PMEVTYPER_EL0<UInt(PMSELR_EL0.SEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMEVTYPERn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && UInt(AArch64.PMSELR_EL0.SEL) != 0x1f
    //              && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
    //         if (!IsFeatureImplemented(FEAT_FGT))
    //             ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
    //         PMCCFILTR_EL0 = X<t,0x40>;
    //     else
    //         PMEVTYPER_EL0<UInt(PMSELR_EL0.SEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
    //         PMCCFILTR_EL0 = X<t,0x40>;
    //     else
    //         PMEVTYPER_EL0<UInt(PMSELR_EL0.SEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (UInt(AArch64.PMSELR_EL0.SEL) == 0x1f)
    //         PMCCFILTR_EL0 = X<t,0x40>;
    //     else
    //         PMEVTYPER_EL0<UInt(PMSELR_EL0.SEL)> = X<t,0x40>;
}


/**
 * PMXEVCNTR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1101', 'op2': '010'})
 * Transformation status: 31 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMXEVCNTR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersSelfHosted())
    {
        if (pGstFeats->fFgt)
            return iemRaiseUndefined(pVCpu);
        ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
        {
            if (!pGstFeats->fFgt)
                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
            else
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        }
        else if (   pGstFeats->fPmuV3p9
                 && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)
                 && (   (AArch64.PMUACR_EL1)<UInt(AArch64.PMSELR_EL0.SEL)> == 0
                     || (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(3)/*ER*/)))
            return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
        else
            PMEVCNTR_EL0<UInt(AArch64.PMSELR_EL0.SEL)> = uValue;
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
        {
            if (!pGstFeats->fFgt)
                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
            else
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        }
        else
            PMEVCNTR_EL0<UInt(AArch64.PMSELR_EL0.SEL)> = uValue;
    }
    else
        PMEVCNTR_EL0<UInt(AArch64.PMSELR_EL0.SEL)> = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersSelfHosted())
    //     if (IsFeatureImplemented(FEAT_FGT))
    //         Undefined()
    //     else
    //         ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMEVCNTRn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
    //         if (!IsFeatureImplemented(FEAT_FGT))
    //             ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_PMUv3p9)
    //              && PMUSERENR_EL0.UEN == '1'
    //              && ((AArch64.PMUACR_EL1)<UInt(AArch64.PMSELR_EL0.SEL)> == '0' || AArch64.PMUSERENR_EL0.ER == '1'))
    //         return;
    //     else
    //         PMEVCNTR_EL0<UInt(PMSELR_EL0.SEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMEVCNTRn_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && UInt(AArch64.PMSELR_EL0.SEL) >= GetNumEventCountersAccessible())
    //         if (!IsFeatureImplemented(FEAT_FGT))
    //             ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMEVCNTR_EL0<UInt(PMSELR_EL0.SEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMEVCNTR_EL0<UInt(PMSELR_EL0.SEL)> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMEVCNTR_EL0<UInt(PMSELR_EL0.SEL)> = X<t,0x40>;
}


/**
 * PMZR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1101', 'op2': '100'})
 * Transformation status: 12 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMZR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3p9)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        ZeroPMUCounters(X<t,0x40>)
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        ZeroPMUCounters(X<t,0x40>)
    }
    else
        ZeroPMUCounters(X<t,0x40>)
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3p9))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMZR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ZeroPMUCounters(X<t,0x40>)
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMZR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ZeroPMUCounters(X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ZeroPMUCounters(X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     ZeroPMUCounters(X<t,0x40>)
}


/**
 * PMUSERENR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMUSERENR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,0),
                                     "PMUSERENR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,0), "PMUSERENR_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMUSERENR_EL0 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMUSERENR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMUSERENR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMUSERENR_EL0 = X<t,0x40>;
}


/**
 * PMOVSSET_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '1110', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMOVSSET_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & UINT32_C(1)/*EN*/)
            && (!pGstFeats->fPmuV3p9 || !(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,3),
                                     "PMOVSSET_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,3),
                                     "PMOVSSET_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,3), "PMOVSSET_EL0", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMOVS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMOVSSET_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HDFGWTR_EL2.PMOVS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMOVSSET_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMOVSSET_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMOVSSET_EL0 = X<t,0x40>;
}


/**
 * PMICNTR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMICNTR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3Icntr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fPmuV3p9
            && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)
            && (AArch64.PMUACR_EL1.F0 == 0 || (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(5)/*IR*/)))
            return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,4,0), "PMICNTR_EL0", uValue, uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,4,0), "PMICNTR_EL0", uValue, uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,4,0), "PMICNTR_EL0", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3_ICNTR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.UEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMICNTR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_PMUv3p9)
    //              && PMUSERENR_EL0.UEN == '1'
    //              && (AArch64.PMUACR_EL1.F0 == '0' || AArch64.PMUSERENR_EL0.IR == '1'))
    //         return;
    //     else
    //         PMICNTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMICNTR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMICNTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMICNTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMICNTR_EL0 = X<t,0x40>;
}


/**
 * PMICFILTR_EL0 - OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1001', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMICFILTR_EL0(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPmuV3Icntr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!(iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fPmuV3p9
            && (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(4)/*UEN*/)
            && (AArch64.PMUACR_EL1.F0 == 0 || (iemCImplHlpGetPmUserEnrEl0(pVCpu) & RT_BIT_32(5)/*IR*/)))
            return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,6,0),
                                     "PMICFILTR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.MdcrEl2.u64 & RT_BIT_32(6)/*TPM*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,6,0),
                                     "PMICFILTR_EL0",
                                     uValue,
                                     uInstrEssence);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,6,0), "PMICFILTR_EL0", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PMUv3_ICNTR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (AArch64.PMUSERENR_EL0.UEN == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMICFILTR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_PMUv3p9)
    //              && PMUSERENR_EL0.UEN == '1'
    //              && (AArch64.PMUACR_EL1.F0 == '0' || AArch64.PMUSERENR_EL0.IR == '1'))
    //         return;
    //     else
    //         PMICFILTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nPMICFILTR_EL0 == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMICFILTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMICFILTR_EL0 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMICFILTR_EL0 = X<t,0x40>;
}


/**
 * VPIDR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0000', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VPIDR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x88, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.VPidrEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x88> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     VPIDR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (!HaveEL(EL2))
    //         return;
    //     VPIDR_EL2 = X<t,0x40>;
}


/**
 * VMPIDR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0000', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VMPIDR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x50, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.VMpidrEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x50> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     VMPIDR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (!HaveEL(EL2))
    //         return;
    //     VMPIDR_EL2 = X<t,0x40>;
}


/**
 * SCTLR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fSrMask)
        pVCpu->cpum.GstCtx.SctlrEl2.u64 = (  (uValue & ~iemGetEffSctlrMaskEl1(pVCpu, pGstFeats))
                                           | (pVCpu->cpum.GstCtx.SctlrEl2.u64 & iemGetEffSctlrMaskEl1(pVCpu, pGstFeats)) );
    else
        pVCpu->cpum.GstCtx.SctlrEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_SRMASK))
    //         SCTLR_EL2 = (X<t,0x40> AND NOT EffectiveSCTLRMASK_EL2()) OR (SCTLR_EL2 AND EffectiveSCTLRMASK_EL2());
    //     else
    //         SCTLR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCTLR_EL2 = X<t,0x40>;
}


/**
 * ACTLR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ACTLR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fSrMask)
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,1),
                                     "ACTLR_EL2",
                                     (uValue & ~EffectiveACTLRMASK_EL2()) | (ACTLR_EL2 & EffectiveACTLRMASK_EL2()),
                                     uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,1), "ACTLR_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_SRMASK))
    //         ACTLR_EL2 = (X<t,0x40> AND NOT EffectiveACTLRMASK_EL2()) OR (ACTLR_EL2 AND EffectiveACTLRMASK_EL2());
    //     else
    //         ACTLR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ACTLR_EL2 = X<t,0x40>;
}


/**
 * SCTLR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR2_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSctlr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fSrMask)
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,3),
                                     "SCTLR2_EL2",
                                     (uValue & ~EffectiveSCTLR2MASK_EL2()) | (SCTLR2_EL2 & EffectiveSCTLR2MASK_EL2()),
                                     uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,3), "SCTLR2_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SCTLR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         SCTLR2_EL2 = (X<t,0x40> AND NOT EffectiveSCTLR2MASK_EL2()) OR (SCTLR2_EL2 AND EffectiveSCTLR2MASK_EL2());
    //     else
    //         SCTLR2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCTLR2_EL2 = X<t,0x40>;
}


/**
 * HCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x78, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.HcrEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x78> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     HCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HCR_EL2 = X<t,0x40>;
}


/**
 * MDCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MDCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.MdcrEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MDCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MDCR_EL2 = X<t,0x40>;
}


/**
 * CPTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CPTR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fSrMask)
        pVCpu->cpum.GstCtx.CptrEl2.u64 = (  (uValue & ~iemGetEffCptrMaskEl2(pVCpu, pGstFeats))
                                          | (pVCpu->cpum.GstCtx.CptrEl2.u64 & iemGetEffCptrMaskEl2(pVCpu, pGstFeats)) );
    else
        pVCpu->cpum.GstCtx.CptrEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         CPTR_EL2 = (X<t,0x40> AND NOT EffectiveCPTRMASK_EL2()) OR (CPTR_EL2 AND EffectiveCPTRMASK_EL2());
    //     else
    //         CPTR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CPTR_EL2 = X<t,0x40>;
}


/**
 * HSTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HSTR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x80, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,3), "HSTR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x80> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     HSTR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HSTR_EL2 = X<t,0x40>;
}


/**
 * HFGRTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HFGRTR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1b8, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,4), "HFGRTR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x1b8> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HFGRTR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HFGRTR_EL2 = X<t,0x40>;
}


/**
 * HFGWTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HFGWTR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1c0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,5), "HFGWTR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x1c0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HFGWTR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HFGWTR_EL2 = X<t,0x40>;
}


/**
 * HFGITR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HFGITR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1c8, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,6), "HFGITR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x1c8> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HFGITR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HFGITR_EL2 = X<t,0x40>;
}


/**
 * HACR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0001', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HACR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,7), "HACR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     HACR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HACR_EL2 = X<t,0x40>;
}


/**
 * ZCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ZCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSve)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(8)/*TZ*/))
        return iemRaiseSystemAccessTrapSve(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 16) & UINT32_C(0x3)/*ZEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapSve(pVCpu, 2);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,0), "ZCR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SVE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.EZ == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.ZEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x19)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.EZ == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x19)
    //     else
    //         ZCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.EZ == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x19)
    //     else
    //         ZCR_EL2 = X<t,0x40>;
}


/**
 * TRFCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRFCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrf)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,1), "TRFCR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRF))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TTRF == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TTRF == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TRFCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TRFCR_EL2 = X<t,0x40>;
}


/**
 * HCRX_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HCRX_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fHcx)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0xa0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,2), "HCRX_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_HCX))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0xa0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.HXEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.HXEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HCRX_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HCRX_EL2 = X<t,0x40>;
}


/**
 * TRCITECR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCITECR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fIte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,3), "TRCITECR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ITE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnITE == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnITE == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TRCITECR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TRCITECR_EL2 = X<t,0x40>;
}


/**
 * SMPRIMAP_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SMPRIMAP_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1f8, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,5), "SMPRIMAP_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x1f8> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SMPRIMAP_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SMPRIMAP_EL2 = X<t,0x40>;
}


/**
 * SMCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SMCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(12)/*TSM*/))
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapSme(pVCpu, 2);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,6), "SMCR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TSM == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.SMEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 0x1d)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         SMCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         SMCR_EL2 = X<t,0x40>;
}


/**
 * SDER32_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SDER32_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL2) && IsFeatureImplemented(FEAT_SEL2) && HaveAArch32EL(EL1)))
    //     Undefined()
    // else if (!HaveEL(EL2) || !IsFeatureImplemented(FEAT_SEL2) || !HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SDER32_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         SDER32_EL2 = X<t,0x40>;
}


/**
 * SCTLRMASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLRMASK_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (iemGetEffSctlrMaskEl1(pVCpu, pGstFeats))
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,0), "SCTLRMASK_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsZero(EffectiveSCTLRMASK_EL2()))
    //         Undefined()
    //     else
    //         SCTLRMASK_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCTLRMASK_EL2 = X<t,0x40>;
}


/**
 * ACTLRMASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ACTLRMASK_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (EffectiveACTLRMASK_EL2())
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,1), "ACTLRMASK_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsZero(EffectiveACTLRMASK_EL2()))
    //         Undefined()
    //     else
    //         ACTLRMASK_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ACTLRMASK_EL2 = X<t,0x40>;
}


/**
 * CPTRMASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CPTRMASK_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (iemGetEffCptrMaskEl2(pVCpu, pGstFeats))
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,2), "CPTRMASK_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsZero(EffectiveCPTRMASK_EL2()))
    //         Undefined()
    //     else
    //         CPTRMASK_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CPTRMASK_EL2 = X<t,0x40>;
}


/**
 * SCTLR2MASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0001', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR2MASK_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (EffectiveSCTLR2MASK_EL2())
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,3), "SCTLR2MASK_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsZero(EffectiveSCTLR2MASK_EL2()))
    //         Undefined()
    //     else
    //         SCTLR2MASK_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCTLR2MASK_EL2 = X<t,0x40>;
}


/**
 * MAIR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MAIR2_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,1,1), "MAIR2_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MAIR2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MAIR2_EL2 = X<t,0x40>;
}


/**
 * MAIR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MAIR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.MairEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     MAIR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MAIR_EL2 = X<t,0x40>;
}


/**
 * PIRE0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PIRE0_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,2), "PIRE0_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PIRE0_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PIRE0_EL2 = X<t,0x40>;
}


/**
 * PIR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PIR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,3), "PIR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PIR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PIR_EL2 = X<t,0x40>;
}


/**
 * POR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_POR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Poe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,4), "POR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         POR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     POR_EL2 = X<t,0x40>;
}


/**
 * S2PIR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_S2PIR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS2Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x2b0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,5), "S2PIR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S2PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x2b0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         S2PIR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     S2PIR_EL2 = X<t,0x40>;
}


/**
 * AMAIR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMAIR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,0), "AMAIR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AMAIR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     AMAIR_EL2 = X<t,0x40>;
}


/**
 * AMAIR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMAIR2_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,1), "AMAIR2_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         AMAIR2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     AMAIR2_EL2 = X<t,0x40>;
}


/**
 * MPAMHCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMHCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x930, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,4,0), "MPAMHCR_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x930> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMHCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMHCR_EL2 = X<t,0x40>;
}


/**
 * MPAMVPMV_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMVPMV_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x938, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,4,1), "MPAMVPMV_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x938> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMVPMV_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMVPMV_EL2 = X<t,0x40>;
}


/**
 * MPAM2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAM2_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,0), "MPAM2_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAM2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAM2_EL2 = X<t,0x40>;
}


/**
 * MPAMBW2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0101', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMBW2_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,4), "MPAMBW2_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMBW2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMBW2_EL2 = X<t,0x40>;
}


/**
 * MPAMBWCAP_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0101', 'op2': '110'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMBWCAP_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl || AArch64.MPAMIDR_EL1.HAS_HCR != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x910, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,6), "MPAMBWCAP_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) && AArch64.MPAMIDR_EL1.HAS_HCR == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x910> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMBWCAP_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMBWCAP_EL2 = X<t,0x40>;
}


/**
 * MPAMVPM0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMVPM0_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x940, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,0), "MPAMVPM0_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1'))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x940> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMVPM0_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMVPM0_EL2 = X<t,0x40>;
}


/**
 * MPAMVPM1_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMVPM1_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x948, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,1), "MPAMVPM1_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 0))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x948> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMVPM1_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMVPM1_EL2 = X<t,0x40>;
}


/**
 * MPAMVPM2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '010'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMVPM2_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x950, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,2), "MPAMVPM2_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x950> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMVPM2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMVPM2_EL2 = X<t,0x40>;
}


/**
 * MPAMVPM3_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '011'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMVPM3_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x958, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,3), "MPAMVPM3_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x958> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMVPM3_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMVPM3_EL2 = X<t,0x40>;
}


/**
 * MPAMVPM4_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '100'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMVPM4_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 3)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x960, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,4), "MPAMVPM4_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x960> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMVPM4_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMVPM4_EL2 = X<t,0x40>;
}


/**
 * MPAMVPM5_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMVPM5_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 4)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x968, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,5), "MPAMVPM5_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 4))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x968> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMVPM5_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMVPM5_EL2 = X<t,0x40>;
}


/**
 * MPAMVPM6_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '110'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMVPM6_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) <= 5)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x970, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,6), "MPAMVPM6_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) > 5))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x970> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMVPM6_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMVPM6_EL2 = X<t,0x40>;
}


/**
 * MPAMVPM7_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '0110', 'op2': '111'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMVPM7_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam || AArch64.MPAMIDR_EL1.HAS_HCR != 1 || UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) != 7)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x978, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,7), "MPAMVPM7_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MPAM) && AArch64.MPAMIDR_EL1.HAS_HCR == '1' && UInt(AArch64.MPAMIDR_EL1.VPMR_MAX) == 7))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x978> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAMVPM7_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MPAMVPM7_EL2 = X<t,0x40>;
}


/**
 * MECID_P0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MECID_P0_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MECID_P0_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MECID_P0_EL2 = X<t,0x40>;
}


/**
 * MECID_A0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MECID_A0_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MECID_A0_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MECID_A0_EL2 = X<t,0x40>;
}


/**
 * MECID_P1_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MECID_P1_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MECID_P1_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MECID_P1_EL2 = X<t,0x40>;
}


/**
 * MECID_A1_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MECID_A1_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MECID_A1_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     MECID_A1_EL2 = X<t,0x40>;
}


/**
 * VMECID_P_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VMECID_P_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         VMECID_P_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     VMECID_P_EL2 = X<t,0x40>;
}


/**
 * VMECID_A_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1010', 'CRm': '1001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VMECID_A_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.MECEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.MECEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         VMECID_A_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     VMECID_A_EL2 = X<t,0x40>;
}


/**
 * VBAR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VBAR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.VBarEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     VBAR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     VBAR_EL2 = X<t,0x40>;
}


/**
 * RMR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_RMR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1 && pGstFeats->fEl2 && (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 2 && pGstFeats->fEl2)
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,0,2), "RMR_EL2", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsHighestEL(EL2))
    //     Undefined()
    // else if (PSTATE.EL == EL1 && IsHighestEL(EL2) && EffectiveHCR_EL2_NVx() IN ('xx1'))
    //     AArch64_SystemAccessTrap(EL2, 0x18)
    // else if (PSTATE.EL == EL2 && IsHighestEL(EL2))
    //     RMR_EL2 = X<t,0x40>;
    // else
    //     Undefined()
}


/**
 * VDISR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VDISR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x500, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,1,1), "VDISR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x500> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     VDISR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     VDISR_EL2 = X<t,0x40>;
}


/**
 * ICH_HCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1011', 'op2': '000'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICH_HCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3 || !pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x4c0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (AArch64.ICC_SRE_EL2.SRE == 0)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,0), "ICH_HCR_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x4c0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         ICH_HCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICH_HCR_EL2 = X<t,0x40>;
}


/**
 * ICH_VMCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1011', 'op2': '111'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICH_VMCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3 || !pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x4c8, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (AArch64.ICC_SRE_EL2.SRE == 0)
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,7), "ICH_VMCR_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x4c8> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (AArch64.ICC_SRE_EL2.SRE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         ICH_VMCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICH_VMCR_EL2 = X<t,0x40>;
}


/**
 * ICC_SRE_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_SRE_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGicV3 || !pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,9,5), "ICC_SRE_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.ICC_SRE_EL3.Enable == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.ICC_SRE_EL3.Enable == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_SRE_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else
    //         ICC_SRE_EL2 = X<t,0x40>;
}


/**
 * CONTEXTIDR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1101', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CONTEXTIDR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fDebugV8p1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,1), "CONTEXTIDR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_Debugv8p1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     CONTEXTIDR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CONTEXTIDR_EL2 = X<t,0x40>;
}


/**
 * TPIDR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1101', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TPIDR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x90, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.aTpIdr[2].u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x90> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     TPIDR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TPIDR_EL2 = X<t,0x40>;
}


/**
 * SCXTNUM_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1101', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCXTNUM_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fCvs2_2 && !pGstFeats->fCsv21p2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,7), "SCXTNUM_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_CSV2_2) || IsFeatureImplemented(FEAT_CSV2_1p2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SCXTNUM_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SCXTNUM_EL2 = X<t,0x40>;
}


/**
 * CNTVOFF_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTVOFF_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x60, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.CntVOffEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x60> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     CNTVOFF_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTVOFF_EL2 = X<t,0x40>;
}


/**
 * CNTPOFF_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTPOFF_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEcvPOff)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1a8, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,0,6), "CNTPOFF_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_ECV_POFF))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x1a8> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ECVEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ECVEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         CNTPOFF_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTPOFF_EL2 = X<t,0x40>;
}


/**
 * CNTHCTL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHCTL_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.CntHCtlEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     CNTHCTL_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTHCTL_EL2 = X<t,0x40>;
}


/**
 * CNTHP_TVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHP_TVAL_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.CntHpCValEl2.u64 = (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) || (!HaveEL(EL3) && HaveEL(EL2) && !IsFeatureImplemented(FEAT_SEL2))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     CNTHP_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    // else if (PSTATE.EL == EL3)
    //     CNTHP_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
}


/**
 * CNTHP_CTL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHP_CTL_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.CntHpCtlEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) || (!HaveEL(EL3) && HaveEL(EL2) && !IsFeatureImplemented(FEAT_SEL2))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     CNTHP_CTL_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTHP_CTL_EL2 = X<t,0x40>;
}


/**
 * CNTHP_CVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHP_CVAL_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fEl2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.CntHpCValEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) || (!HaveEL(EL3) && HaveEL(EL2) && !IsFeatureImplemented(FEAT_SEL2))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     CNTHP_CVAL_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTHP_CVAL_EL2 = X<t,0x40>;
}


/**
 * CNTHV_TVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHV_TVAL_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fVhe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu,
                                 ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,2),
                                 "CNTHV_CVAL_EL2",
                                 (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu),
                                 uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_VHE) && (HaveEL(EL3) || (!HaveEL(EL3) && !IsFeatureImplemented(FEAT_SEL2)))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     CNTHV_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    // else if (PSTATE.EL == EL3)
    //     CNTHV_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
}


/**
 * CNTHV_CTL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHV_CTL_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fVhe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,1), "CNTHV_CTL_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_VHE) && (HaveEL(EL3) || (!HaveEL(EL3) && !IsFeatureImplemented(FEAT_SEL2)))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     CNTHV_CTL_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTHV_CTL_EL2 = X<t,0x40>;
}


/**
 * CNTHV_CVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHV_CVAL_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fVhe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,2), "CNTHV_CVAL_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_VHE) && (HaveEL(EL3) || (!HaveEL(EL3) && !IsFeatureImplemented(FEAT_SEL2)))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     CNTHV_CVAL_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     CNTHV_CVAL_EL2 = X<t,0x40>;
}


/**
 * CNTHVS_TVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHVS_TVAL_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_SEL2) && IsFeatureImplemented(FEAT_VHE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         CNTHVS_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         CNTHVS_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
}


/**
 * CNTHVS_CTL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHVS_CTL_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_SEL2) && IsFeatureImplemented(FEAT_VHE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         CNTHVS_CTL_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         CNTHVS_CTL_EL2 = X<t,0x40>;
}


/**
 * CNTHVS_CVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHVS_CVAL_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_SEL2) && IsFeatureImplemented(FEAT_VHE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         CNTHVS_CVAL_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         CNTHVS_CVAL_EL2 = X<t,0x40>;
}


/**
 * CNTHPS_TVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHPS_TVAL_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL2) && IsFeatureImplemented(FEAT_SEL2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         CNTHPS_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         CNTHPS_CVAL_EL2 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
}


/**
 * CNTHPS_CTL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHPS_CTL_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SEL2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         CNTHPS_CTL_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         CNTHPS_CTL_EL2 = X<t,0x40>;
}


/**
 * CNTHPS_CVAL_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1110', 'CRm': '0101', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTHPS_CVAL_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL2) && IsFeatureImplemented(FEAT_SEL2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         CNTHPS_CVAL_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         CNTHPS_CVAL_EL2 = X<t,0x40>;
}


/**
 * TTBR0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TTBR0_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.Ttbr0El2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     TTBR0_EL2<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TTBR0_EL2<[0x3f:0]> = X<t,0x40>;
}


/**
 * TTBR1_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TTBR1_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fVhe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.Ttbr1El2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_VHE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     TTBR1_EL2<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TTBR1_EL2<[0x3f:0]> = X<t,0x40>;
}


/**
 * TCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 2 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fSrMask)
        pVCpu->cpum.GstCtx.TcrEl2.u64 = (  (uValue & ~EffectiveTCRMASK_EL2())
                                         | (pVCpu->cpum.GstCtx.TcrEl2.u64 & EffectiveTCRMASK_EL2()) );
    else
        pVCpu->cpum.GstCtx.TcrEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_SRMASK))
    //         TCR_EL2 = (X<t,0x40> AND NOT EffectiveTCRMASK_EL2()) OR (TCR_EL2 AND EffectiveTCRMASK_EL2());
    //     else
    //         TCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TCR_EL2 = X<t,0x40>;
}


/**
 * TCR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 3 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCR2_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTcr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fSrMask)
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,3),
                                     "TCR2_EL2",
                                     (uValue & ~EffectiveTCR2MASK_EL2()) | (TCR2_EL2 & EffectiveTCR2MASK_EL2()),
                                     uInstrEssence);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,3), "TCR2_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TCR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (IsFeatureImplemented(FEAT_SRMASK))
    //         TCR2_EL2 = (X<t,0x40> AND NOT EffectiveTCR2MASK_EL2()) OR (TCR2_EL2 AND EffectiveTCR2MASK_EL2());
    //     else
    //         TCR2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TCR2_EL2 = X<t,0x40>;
}


/**
 * VTTBR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VTTBR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x20, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.VTtbrEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x20> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     VTTBR_EL2<[0x3f:0]> = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     VTTBR_EL2<[0x3f:0]> = X<t,0x40>;
}


/**
 * VTCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VTCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x40, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.VTcrEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x40> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     VTCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     VTCR_EL2 = X<t,0x40>;
}


/**
 * VNCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VNCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fNv2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0xb0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,2,0), "VNCR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_NV2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0xb0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     VNCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     VNCR_EL2 = X<t,0x40>;
}


/**
 * HDBSSBR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HDBSSBR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fHdbss)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x2e0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,2), "HDBSSBR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_HDBSS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x2e0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.HDBSSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.HDBSSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HDBSSBR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HDBSSBR_EL2 = X<t,0x40>;
}


/**
 * HDBSSPROD_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HDBSSPROD_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fHdbss)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x300, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,3), "HDBSSPROD_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_HDBSS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x300> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.HDBSSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.HDBSSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HDBSSPROD_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HDBSSPROD_EL2 = X<t,0x40>;
}


/**
 * HACDBSBR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0011', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HACDBSBR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fHacdbs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x2f0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,4), "HACDBSBR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_HACDBS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x2f0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.HACDBSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.HACDBSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HACDBSBR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HACDBSBR_EL2 = X<t,0x40>;
}


/**
 * HACDBSCONS_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HACDBSCONS_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fHacdbs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x308, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,5), "HACDBSCONS_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_HACDBS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x308> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.HACDBSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.HACDBSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HACDBSCONS_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HACDBSCONS_EL2 = X<t,0x40>;
}


/**
 * GCSCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GCSCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,5,0), "GCSCR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GCSCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     GCSCR_EL2 = X<t,0x40>;
}


/**
 * GCSPR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GCSPR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,5,1), "GCSPR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GCSPR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     GCSPR_EL2 = X<t,0x40>;
}


/**
 * VSTTBR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VSTTBR_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SEL2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x30> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         VSTTBR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         VSTTBR_EL2 = X<t,0x40>;
}


/**
 * VSTCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0110', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VSTCR_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SEL2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x48> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Secure))
    //         Undefined()
    //     else
    //         VSTCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.SCR_EL3.EEL2 == '0')
    //         Undefined()
    //     else
    //         VSTCR_EL2 = X<t,0x40>;
}


/**
 * TCRMASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0111', 'op2': '010'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCRMASK_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (EffectiveTCRMASK_EL2())
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,2), "TCRMASK_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsZero(EffectiveTCRMASK_EL2()))
    //         Undefined()
    //     else
    //         TCRMASK_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TCRMASK_EL2 = X<t,0x40>;
}


/**
 * TCR2MASK_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 1 - incomplete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCR2MASK_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(pVCpu, uValue, uInstrEssence);
#ifdef IEM_SYSREG_TODO
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (EffectiveTCR2MASK_EL2())
        return iemRaiseUndefined(pVCpu);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,3), "TCR2MASK_EL2", uValue, uInstrEssence);
#endif
    return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (!IsZero(EffectiveTCR2MASK_EL2()))
    //         Undefined()
    //     else
    //         TCR2MASK_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TCR2MASK_EL2 = X<t,0x40>;
}


/**
 * DACR32_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_DACR32_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAa32El1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,0,0), "DACR32_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     DACR32_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     DACR32_EL2 = X<t,0x40>;
}


/**
 * HDFGRTR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HDFGRTR2_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x1a0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HDFGRTR2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HDFGRTR2_EL2 = X<t,0x40>;
}


/**
 * HDFGWTR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HDFGWTR2_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x1b0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HDFGWTR2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HDFGWTR2_EL2 = X<t,0x40>;
}


/**
 * HFGRTR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HFGRTR2_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x2c0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HFGRTR2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HFGRTR2_EL2 = X<t,0x40>;
}


/**
 * HFGWTR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HFGWTR2_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x2c8> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HFGWTR2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HFGWTR2_EL2 = X<t,0x40>;
}


/**
 * HDFGRTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HDFGRTR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1d0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,4), "HDFGRTR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x1d0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HDFGRTR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HDFGRTR_EL2 = X<t,0x40>;
}


/**
 * HDFGWTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HDFGWTR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1d8, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,5), "HDFGWTR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x1d8> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HDFGWTR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HDFGWTR_EL2 = X<t,0x40>;
}


/**
 * HAFGRTR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HAFGRTR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAmuV1 || !pGstFeats->fFgt)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1e8, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,6), "HAFGRTR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_AMUv1) && IsFeatureImplemented(FEAT_FGT)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x1e8> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HAFGRTR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HAFGRTR_EL2 = X<t,0x40>;
}


/**
 * HFGITR2_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0011', 'CRm': '0001', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HFGITR2_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_FGT2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x310> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FGTEn2 == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         HFGITR2_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HFGITR2_EL2 = X<t,0x40>;
}


/**
 * SPSR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPSR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/)
            && (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseExlockException(pVCpu);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            pVCpu->cpum.GstCtx.Spsr.u64 = uValue;
        else if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        else
            return iemRaiseUndefined(pVCpu);
    }
    else
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/))
            return iemRaiseExlockException(pVCpu);
        pVCpu->cpum.GstCtx.SpsrEl2.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   IsFeatureImplemented(FEAT_GCS)
    //         && GetCurrentEXLOCKEN()
    //         && !Halted()
    //         && PSTATE.EXLOCK == '1'
    //         && EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         EXLOCKException()
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         SPSR_EL1 = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1')
    //         EXLOCKException()
    //     else
    //         SPSR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPSR_EL2 = X<t,0x40>;
}


/**
 * ELR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ELR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/)
            && (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseExlockException(pVCpu);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            pVCpu->cpum.GstCtx.Elr.u64 = uValue;
        else if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        else
            return iemRaiseUndefined(pVCpu);
    }
    else
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/))
            return iemRaiseExlockException(pVCpu);
        pVCpu->cpum.GstCtx.ElrEl2.u64 = uValue;
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (   IsFeatureImplemented(FEAT_GCS)
    //         && GetCurrentEXLOCKEN()
    //         && !Halted()
    //         && PSTATE.EXLOCK == '1'
    //         && EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         EXLOCKException()
    //     else if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         ELR_EL1 = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1')
    //         EXLOCKException()
    //     else
    //         ELR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ELR_EL2 = X<t,0x40>;
}


/**
 * SP_EL1 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SP_EL1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x240, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.aSpReg[1].u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x240> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     SP_EL1 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SP_EL1 = X<t,0x40>;
}


/**
 * SPSR_irq - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPSR_irq(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,0), "SPSR_irq", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     SPSR_irq = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPSR_irq = X<t,0x40>;
}


/**
 * SPSR_abt - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPSR_abt(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,1), "SPSR_abt", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     SPSR_abt = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPSR_abt = X<t,0x40>;
}


/**
 * SPSR_und - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPSR_und(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,2), "SPSR_und", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     SPSR_und = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPSR_und = X<t,0x40>;
}


/**
 * SPSR_fiq - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0100', 'CRm': '0011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPSR_fiq(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,3), "SPSR_fiq", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     SPSR_fiq = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     SPSR_fiq = X<t,0x40>;
}


/**
 * IFSR32_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_IFSR32_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAa32El1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,0,1), "IFSR32_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     IFSR32_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     IFSR32_EL2 = X<t,0x40>;
}


/**
 * AFSR0_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AFSR0_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,0), "AFSR0_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AFSR0_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     AFSR0_EL2 = X<t,0x40>;
}


/**
 * AFSR1_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AFSR1_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,1), "AFSR1_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AFSR1_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     AFSR1_EL2 = X<t,0x40>;
}


/**
 * ESR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ESR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            pVCpu->cpum.GstCtx.Esr.u64 = uValue;
        else if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        else
            return iemRaiseUndefined(pVCpu);
    }
    else
        pVCpu->cpum.GstCtx.EsrEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         ESR_EL1 = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     ESR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     ESR_EL2 = X<t,0x40>;
}


/**
 * VSESR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VSESR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fRas)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x508, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,2,3), "VSESR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RAS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         NVMem<0x508> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     VSESR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     VSESR_EL2 = X<t,0x40>;
}


/**
 * FPEXC32_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_FPEXC32_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAa32El1)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (   (!pGstFeats->fVhe || !pGstFeats->fEl2 || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        && (pVCpu->cpum.GstCtx.CptrEl2.u64 & RT_BIT_32(10)/*TFP*/))
        return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 20) & UINT32_C(0x3)/*FPEN*/) & 1) == 0)
        return iemRaiseSystemAccessTrapAdvSimdFpAccessA64(pVCpu, 2);
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,3,0), "FPEXC32_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TFP == '1')
    //         Undefined()
    //     else if (!ELIsInHost(EL2) && AArch64.CPTR_EL2.TFP == '1')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (ELIsInHost(EL2) && AArch64.CPTR_EL2.FPEN IN 'x0')
    //         AArch64_SystemAccessTrap(EL2, 7)
    //     else if (HaveEL(EL3) && AArch64.CPTR_EL3.TFP == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPEXC32_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.TFP == '1')
    //         AArch64_SystemAccessTrap(EL3, 7)
    //     else
    //         FPEXC32_EL2 = X<t,0x40>;
}


/**
 * TFSR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0101', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TFSR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
        {
            if (pGstFeats->fEl2 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(56)/*ATA*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemCImplA64_msr_novar(pVCpu,
                                         ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,0),
                                         "TFSR_EL1",
                                         uValue,
                                         uInstrEssence);
        }
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,6,0), "TFSR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //             Undefined()
    //         else if (EL2Enabled() && AArch64.HCR_EL2.ATA == '0')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             TFSR_EL1 = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TFSR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TFSR_EL2 = X<t,0x40>;
}


/**
 * FAR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0110', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_FAR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 5) == 5)
            pVCpu->cpum.GstCtx.Far.u64 = uValue;
        else if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        else
            return iemRaiseUndefined(pVCpu);
    }
    else
        pVCpu->cpum.GstCtx.FarEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('1x1'))
    //         FAR_EL1 = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     FAR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     FAR_EL2 = X<t,0x40>;
}


/**
 * HPFAR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0110', 'CRm': '0000', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_HPFAR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    pVCpu->cpum.GstCtx.HpFarEl2.u64 = uValue;
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     HPFAR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     HPFAR_EL2 = X<t,0x40>;
}


/**
 * PFAR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0110', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PFAR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPfar)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,6,0,5), "PFAR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PFAR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PFAREn == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.SCR_EL3.PFAREn == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PFAR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PFAR_EL2 = X<t,0x40>;
}


/**
 * PMBSR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1001', 'CRm': '1010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMBSR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpeExc)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,10,3), "PMBSR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE_EXC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.PMSEE == '00')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.PMSEE == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMBSR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMBSR_EL2 = X<t,0x40>;
}


/**
 * TRBSR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1001', 'CRm': '1011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRBSR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbeExc)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,11,3), "TRBSR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE_EXC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //             || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TRBEE == '00')
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.TRBEE == '00')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TRBSR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     TRBSR_EL2 = X<t,0x40>;
}


/**
 * PMSCR_EL2 - OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1001', 'CRm': '1001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSCR_EL2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,9,0), "PMSCR_EL2", uValue, uInstrEssence);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (   HaveEL(EL3)
    //         && EL3SDDUndefPriority()
    //         && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //             || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //             || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         Undefined()
    //     else if (   HaveEL(EL3)
    //              && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                  || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                  || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PMSCR_EL2 = X<t,0x40>;
    // else if (PSTATE.EL == EL3)
    //     PMSCR_EL2 = X<t,0x40>;
}


/**
 * SCTLR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x110, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Sctlr.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x110> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         SCTLR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         SCTLR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * ACTLR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ACTLR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x118, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Actlr.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x118> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         ACTLR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         ACTLR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * CPACR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CPACR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x100, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Cpacr.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x100> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TCPAC == '1')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.CPTR_EL3.TCPAC == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             CPACR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         CPACR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * SCTLR2_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR2_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSctlr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x278, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3), "SCTLR2_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SCTLR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x278> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SCTLR2En == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SCTLR2En == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             SCTLR2_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         SCTLR2_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * ZCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ZCR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSve)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1e0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if ((((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 16) & UINT32_C(0x3)/*ZEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSve(pVCpu, 2);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,0), "ZCR_EL1", uValue, uInstrEssence);
    }
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SVE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x1e0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.EZ == '0')
    //             Undefined()
    //         else if (AArch64.CPTR_EL2.ZEN IN 'x0')
    //             AArch64_SystemAccessTrap(EL2, 0x19)
    //         else if (HaveEL(EL3) && AArch64.CPTR_EL3.EZ == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x19)
    //         else
    //             ZCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         if (AArch64.CPTR_EL3.EZ == '0')
    //             AArch64_SystemAccessTrap(EL3, 0x19)
    //         else
    //             ZCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * TRFCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRFCR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrf)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x880, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,1), "TRFCR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRF))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x880> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TTRF == '1')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MDCR_EL3.TTRF == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             TRFCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         TRFCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * TRCITECR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRCITECR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fIte || !pGstFeats->fTrcSr)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x888, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,3),
                                     "TRCITECR_EL1",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_ITE) && IsFeatureImplemented(FEAT_TRC_SR)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x888> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnITE == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnITE == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             TRCITECR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         TRCITECR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * SMCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SMCR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSme)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x1f0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
    {
        if ((((pVCpu->cpum.GstCtx.CptrEl2.u64 >> 24) & UINT32_C(0x3)/*SMEN*/) & 1) == 0)
            return iemRaiseSystemAccessTrapSme(pVCpu, 2);
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,6), "SMCR_EL1", uValue, uInstrEssence);
    }
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x1f0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.ESM == '0')
    //             Undefined()
    //         else if (AArch64.CPTR_EL2.SMEN IN 'x0')
    //             AArch64_SystemAccessTrap(EL2, 0x1d)
    //         else if (HaveEL(EL3) && AArch64.CPTR_EL3.ESM == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x1d)
    //         else
    //             SMCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         if (AArch64.CPTR_EL3.ESM == '0')
    //             AArch64_SystemAccessTrap(EL3, 0x1d)
    //         else
    //             SMCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * SCTLRMASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLRMASK_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x318, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,0),
                                     "SCTLRMASK_EL1",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x318> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             SCTLRMASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         SCTLRMASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * ACTLRMASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ACTLRMASK_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x340, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,1),
                                     "ACTLRMASK_EL1",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x340> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             ACTLRMASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         ACTLRMASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * CPACRMASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CPACRMASK_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x320, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,2),
                                     "CPACRMASK_EL1",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x320> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             CPACRMASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         CPACRMASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * SCTLR2MASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0001', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR2MASK_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x328, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,3),
                                     "SCTLR2MASK_EL1",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x328> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             SCTLR2MASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         SCTLR2MASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * MAIR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MAIR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x140, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Mair.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x140> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         MAIR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         MAIR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * MAIR2_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MAIR2_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x280, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,1), "MAIR2_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x280> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             MAIR2_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         MAIR2_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * PIRE0_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PIRE0_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x290, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,2), "PIRE0_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x290> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             PIRE0_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         PIRE0_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * PIR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PIR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Pie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x2a0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,3), "PIR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x2a0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             PIR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         PIR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * POR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_POR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fS1Poe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x2a8, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,4), "POR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x2a8> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PIEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.PIEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             POR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         POR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * AMAIR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMAIR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x148, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Amair.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x148> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AMAIR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         AMAIR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * AMAIR2_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMAIR2_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fAie)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x288, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,3,1), "AMAIR2_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x288> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AIEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.AIEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AMAIR2_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         AMAIR2_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * MPAM1_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAM1_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpam)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x900, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,0), "MPAM1_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x900> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             MPAM1_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         MPAM1_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * MPAMBW1_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1010', 'CRm': '0101', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMBW1_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMpamPeBwCtrl)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x908, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,4),
                                     "MPAMBW1_EL1",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x908> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             Undefined()
    //         else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.MPAM3_EL3.TRAPLOWER == '1')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (HaveEL(EL3) && AArch64.MPAMBW3_EL3.nTRAPLOWER == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             MPAMBW1_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         MPAMBW1_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * VBAR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VBAR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x250, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.VBar.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x250> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         VBAR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         VBAR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * CONTEXTIDR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1101', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CONTEXTIDR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x108, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.ContextIdr.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x108> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         CONTEXTIDR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         CONTEXTIDR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * SCXTNUM_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1101', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCXTNUM_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fCvs2_2 && !pGstFeats->fCsv21p2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x188, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,7),
                                     "SCXTNUM_EL1",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_CSV2_2) || IsFeatureImplemented(FEAT_CSV2_1p2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x188> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnSCXT == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.EnSCXT == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             SCXTNUM_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         SCXTNUM_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * CNTKCTL_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTKCTL_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.CntKCtl.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         CNTKCTL_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         CNTKCTL_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * CNTP_TVAL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTP_TVAL_EL02(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                     "CNTP_CVAL_EL0",
                                     (int64_t)(int32_t)(uValue) + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu),
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         CNTP_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         CNTP_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    //     else
    //         Undefined()
}


/**
 * CNTP_CTL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTP_CTL_EL02(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
        {
            if (   pGstFeats->fEl2
                && (   !pGstFeats->fVhe
                    || !pGstFeats->fEl2
                    || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                    || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(15)/*EL1NVPCT*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x180, uValue);
        }
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,1),
                                     "CNTP_CTL_EL0",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL1NVPCT == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             NVMem<0x180> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         CNTP_CTL_EL0 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         CNTP_CTL_EL0 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * CNTP_CVAL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTP_CVAL_EL02(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
        {
            if (   pGstFeats->fEl2
                && (   !pGstFeats->fVhe
                    || !pGstFeats->fEl2
                    || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                    || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(15)/*EL1NVPCT*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x178, uValue);
        }
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2),
                                     "CNTP_CVAL_EL0",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL1NVPCT == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             NVMem<0x178> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         CNTP_CVAL_EL0 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         CNTP_CVAL_EL0 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * CNTV_TVAL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTV_TVAL_EL02(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.CntvCValEl0 = (  (int64_t)(int32_t)(uValue)
                                          + iemCImplHlpGetPhysicalSystemTimerCount(pVCpu)
                                          - pVCpu->cpum.GstCtx.CntVOffEl2.u64 );
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         CNTV_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt() - CNTVOFF_EL2;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         CNTV_CVAL_EL0 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt() - CNTVOFF_EL2;
    //     else
    //         Undefined()
}


/**
 * CNTV_CTL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTV_CTL_EL02(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
        {
            if (   pGstFeats->fEl2
                && (   !pGstFeats->fVhe
                    || !pGstFeats->fEl2
                    || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                    || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(16)/*EL1NVVCT*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x170, uValue);
        }
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.CntvCtlEl0 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL1NVVCT == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             NVMem<0x170> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         CNTV_CTL_EL0 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         CNTV_CTL_EL0 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * CNTV_CVAL_EL02 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1110', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTV_CVAL_EL02(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
        {
            if (   pGstFeats->fEl2
                && (   !pGstFeats->fVhe
                    || !pGstFeats->fEl2
                    || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                    || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                && (pVCpu->cpum.GstCtx.CntHCtlEl2.u64 & RT_BIT_32(16)/*EL1NVVCT*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x168, uValue);
        }
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.CntvCValEl0 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.CNTHCTL_EL2.EL1NVVCT == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             NVMem<0x168> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         CNTV_CVAL_EL0 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         CNTV_CVAL_EL0 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * TTBR0_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TTBR0_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x200, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Ttbr0.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x200> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         TTBR0_EL1<[0x3f:0]> = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         TTBR0_EL1<[0x3f:0]> = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * TTBR1_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TTBR1_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x210, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Ttbr1.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x210> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         TTBR1_EL1<[0x3f:0]> = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         TTBR1_EL1<[0x3f:0]> = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * TCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x120, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Tcr.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x120> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         TCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         TCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * TCR2_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCR2_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTcr2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x270, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3), "TCR2_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TCR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x270> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.TCR2En == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.TCR2En == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             TCR2_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         TCR2_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * GCSCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GCSCR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x8d0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,0), "GCSCR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x8d0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             GCSCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         GCSCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * GCSPR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GCSPR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x8c0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,1), "GCSPR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x8c0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.GCSEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.GCSEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             GCSPR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         GCSPR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * TCRMASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0111', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCRMASK_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x330, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,2), "TCRMASK_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x330> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             TCRMASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         TCRMASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * TCR2MASK_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCR2MASK_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSrMask)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x338, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu,
                                     ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,3),
                                     "TCR2MASK_EL1",
                                     uValue,
                                     uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SRMASK))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x338> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.SRMASKEn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.SRMASKEn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             TCR2MASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         TCR2MASK_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * SPSR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPSR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x160, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Spsr.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x160> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         SPSR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         SPSR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * ELR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0100', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ELR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x230, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Elr.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x230> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         ELR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         ELR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * AFSR0_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0101', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AFSR0_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x128, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Afsr0.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x128> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AFSR0_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         AFSR0_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * AFSR1_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0101', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AFSR1_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x130, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Afsr1.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x130> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AFSR1_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         AFSR1_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * ESR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0101', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ESR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x138, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Esr.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x138> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         ESR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         ESR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * TFSR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0101', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TFSR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x190, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,0), "TFSR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x190> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ATA == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.ATA == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             TFSR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         TFSR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * FAR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0110', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_FAR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x220, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        pVCpu->cpum.GstCtx.Far.u64 = uValue;
    else
        return iemRaiseUndefined(pVCpu);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x220> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         FAR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         FAR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * PFAR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0110', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PFAR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPfar)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x2d0, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,6,0,5), "PFAR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PFAR))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x2d0> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.PFAREn == '0')
    //             Undefined()
    //         else if (HaveEL(EL3) && AArch64.SCR_EL3.PFAREn == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             PFAR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         PFAR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * PMBSR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1001', 'CRm': '1010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMBSR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x820, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,3), "PMBSR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x820> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (   HaveEL(EL3)
    //             && EL3SDDUndefPriority()
    //             && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                 || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                 || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //             Undefined()
    //         else if (   HaveEL(EL3)
    //                  && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                      || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                      || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             PMBSR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         PMBSR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * TRBSR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1001', 'CRm': '1011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRBSR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTrbeExc)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x860, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,3), "TRBSR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TRBE_EXC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x860> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (   HaveEL(EL3)
    //             && EL3SDDUndefPriority()
    //             && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                 || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                 || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //             Undefined()
    //         else if (   HaveEL(EL3)
    //                  && (   AArch64.MDCR_EL3.NSTB<0> == '0'
    //                      || AArch64.MDCR_EL3.NSTB<1> != AArch64.SCR_EL3.NS
    //                      || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSTBE != AArch64.SCR_EL3.NSE)))
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else if (   IsFeatureImplemented(FEAT_TRBE_EXT)
    //                  && AArch64.OSLSR_EL1.OSLK == '0'
    //                  && HaltingAllowed()
    //                  && ext.EDSCR2.TTA == '1')
    //             Halt(DebugHalt_SoftwareAccess)
    //         else
    //             TRBSR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         if (   IsFeatureImplemented(FEAT_TRBE_EXT)
    //             && AArch64.OSLSR_EL1.OSLK == '0'
    //             && HaltingAllowed()
    //             && ext.EDSCR2.TTA == '1')
    //             Halt(DebugHalt_SoftwareAccess)
    //         else
    //             TRBSR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * PMSCR_EL12 - OrderedDict({'op0': '11', 'op1': '101', 'CRn': '1001', 'CRm': '1001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMSCR_EL12(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemGetEffHcrEl2NVx(pVCpu, pGstFeats) == 5)
            return iemCImplHlpNVMemWriteU64(pVCpu, 0x828, uValue);
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplA64_msr_novar(pVCpu, ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,0), "PMSCR_EL1", uValue, uInstrEssence);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() == '101')
    //         NVMem<0x828> = X<t,0x40>;
    //     else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         if (   HaveEL(EL3)
    //             && EL3SDDUndefPriority()
    //             && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                 || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                 || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //             Undefined()
    //         else if (   HaveEL(EL3)
    //                  && (   AArch64.MDCR_EL3.NSPB<0> == '0'
    //                      || AArch64.MDCR_EL3.NSPB<1> != AArch64.SCR_EL3.NS
    //                      || (IsFeatureImplemented(FEAT_RME) && AArch64.MDCR_EL3.NSPBE != AArch64.SCR_EL3.NSE)))
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             PMSCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL2))
    //         PMSCR_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
}


/**
 * SCTLR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.SCTLR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SCTLR_EL3 = X<t,0x40>;
}


/**
 * ACTLR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ACTLR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.ACTLR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ACTLR_EL3 = X<t,0x40>;
}


/**
 * SCTLR2_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCTLR2_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SCTLR2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.SCTLR2_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         SCTLR2_EL3 = X<t,0x40>;
}


/**
 * SCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     SCR_EL3 = X<t,0x40>;
}


/**
 * SDER32_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SDER32_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) && HaveAArch32EL(EL1)))
    //     Undefined()
    // else if (!HaveEL(EL3) || !HaveAArch32EL(EL1))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     SDER32_EL3 = X<t,0x40>;
}


/**
 * CPTR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CPTR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     CPTR_EL3 = X<t,0x40>;
}


/**
 * FGWTE3_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_FGWTE3_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) && IsFeatureImplemented(FEAT_FGWTE3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     FGWTE3_EL3 = X<t,0x40>;
}


/**
 * ZCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ZCR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SVE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.EZ == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x19)
    //     else
    //         ZCR_EL3 = X<t,0x40>;
}


/**
 * SMCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SMCR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_SME) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.CPTR_EL3.ESM == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x1d)
    //     else
    //         SMCR_EL3 = X<t,0x40>;
}


/**
 * MDCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0001', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MDCR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.MDCR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MDCR_EL3 = X<t,0x40>;
}


/**
 * MAIR2_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MAIR2_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.MAIR2_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MAIR2_EL3 = X<t,0x40>;
}


/**
 * MECID_RL_A_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '1010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MECID_RL_A_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.MECID_RL_A_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MECID_RL_A_EL3 = X<t,0x40>;
}


/**
 * MAIR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MAIR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.MAIR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MAIR_EL3 = X<t,0x40>;
}


/**
 * PIR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PIR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1PIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.PIR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         PIR_EL3 = X<t,0x40>;
}


/**
 * POR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_POR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_S1POE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     POR_EL3 = X<t,0x40>;
}


/**
 * AMAIR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMAIR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.AMAIR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         AMAIR_EL3 = X<t,0x40>;
}


/**
 * AMAIR2_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AMAIR2_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_AIE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.AMAIR2_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         AMAIR2_EL3 = X<t,0x40>;
}


/**
 * MPAM3_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAM3_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.MPAM3_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         MPAM3_EL3 = X<t,0x40>;
}


/**
 * MPAMBW3_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1010', 'CRm': '0101', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MPAMBW3_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     MPAMBW3_EL3 = X<t,0x40>;
}


/**
 * VBAR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VBAR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.VBAR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         VBAR_EL3 = X<t,0x40>;
}


/**
 * RMR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_RMR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL3 && IsHighestEL(EL3))
    //     RMR_EL3 = X<t,0x40>;
    // else
    //     Undefined()
}


/**
 * VDISR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VDISR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_E3DSE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     VDISR_EL3 = X<t,0x40>;
}


/**
 * ICC_CTLR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '1100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_CTLR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_CTLR_EL3 = X<t,0x40>;
}


/**
 * ICC_SRE_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '1100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_SRE_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     ICC_SRE_EL3 = X<t,0x40>;
}


/**
 * ICC_IGRPEN1_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1100', 'CRm': '1100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ICC_IGRPEN1_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.ICC_SRE_EL3.SRE == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         ICC_IGRPEN1_EL3 = X<t,0x40>;
}


/**
 * TPIDR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1101', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TPIDR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.TPIDR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TPIDR_EL3 = X<t,0x40>;
}


/**
 * SCXTNUM_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1101', 'CRm': '0000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SCXTNUM_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(HaveEL(EL3) && (IsFeatureImplemented(FEAT_CSV2_2) || IsFeatureImplemented(FEAT_CSV2_1p2))))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     SCXTNUM_EL3 = X<t,0x40>;
}


/**
 * TTBR0_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TTBR0_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.TTBR0_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TTBR0_EL3 = X<t,0x40>;
}


/**
 * TCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TCR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.TCR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         TCR_EL3 = X<t,0x40>;
}


/**
 * GPTBR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GPTBR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.GPTBR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GPTBR_EL3 = X<t,0x40>;
}


/**
 * GPCBW_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GPCBW_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME_GPC3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.GPCBW_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GPCBW_EL3 = X<t,0x40>;
}


/**
 * GPCCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GPCCR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.GPCCR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GPCCR_EL3 = X<t,0x40>;
}


/**
 * GCSCR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GCSCR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GCS) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.GCSCR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GCSCR_EL3 = X<t,0x40>;
}


/**
 * GCSPR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0010', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_GCSPR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_GCS) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.GCSPR_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         GCSPR_EL3 = X<t,0x40>;
}


/**
 * SPSR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0100', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SPSR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1')
    //         EXLOCKException()
    //     else
    //         SPSR_EL3 = X<t,0x40>;
}


/**
 * ELR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0100', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ELR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1')
    //         EXLOCKException()
    //     else
    //         ELR_EL3 = X<t,0x40>;
}


/**
 * SP_EL2 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0100', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_SP_EL2(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     SP_EL2 = X<t,0x40>;
}


/**
 * AFSR0_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0101', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AFSR0_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.AFSR0_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         AFSR0_EL3 = X<t,0x40>;
}


/**
 * AFSR1_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0101', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_AFSR1_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_FGWTE3) && AArch64.FGWTE3_EL3.AFSR1_EL3 == '1')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         AFSR1_EL3 = X<t,0x40>;
}


/**
 * ESR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0101', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_ESR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     ESR_EL3 = X<t,0x40>;
}


/**
 * VSESR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0101', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_VSESR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_E3DSE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     VSESR_EL3 = X<t,0x40>;
}


/**
 * TFSR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0101', 'CRm': '0110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TFSR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     TFSR_EL3 = X<t,0x40>;
}


/**
 * FAR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0110', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_FAR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     FAR_EL3 = X<t,0x40>;
}


/**
 * MFAR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '0110', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_MFAR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_PFAR) || IsFeatureImplemented(FEAT_RME)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     MFAR_EL3 = X<t,0x40>;
}


/**
 * PMBSR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1001', 'CRm': '1010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_PMBSR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_SPE_EXC) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     PMBSR_EL3 = X<t,0x40>;
}


/**
 * TRBSR_EL3 - OrderedDict({'op0': '11', 'op1': '110', 'CRn': '1001', 'CRm': '1011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_TRBSR_EL3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TRBE_EXC) && HaveEL(EL3)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     TRBSR_EL3 = X<t,0x40>;
}


/**
 * CNTPS_TVAL_EL1 - OrderedDict({'op0': '11', 'op1': '111', 'CRn': '1110', 'CRm': '0010', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTPS_TVAL_EL1(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ST == '0')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.EEL2 == '1')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.ST == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             CNTPS_CVAL_EL1 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     CNTPS_CVAL_EL1 = SignExtend((X<t,0x40>)<[0x1f:0]>, 0x40) + PhysicalCountInt();
}


/**
 * CNTPS_CTL_EL1 - OrderedDict({'op0': '11', 'op1': '111', 'CRn': '1110', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTPS_CTL_EL1(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ST == '0')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.EEL2 == '1')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.ST == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             CNTPS_CTL_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     CNTPS_CTL_EL1 = X<t,0x40>;
}


/**
 * CNTPS_CVAL_EL1 - OrderedDict({'op0': '11', 'op1': '111', 'CRn': '1110', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_msr_CNTPS_CVAL_EL1(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!HaveEL(EL3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && AArch64.SCR_EL3.NS == '0')
    //         if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.ST == '0')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.EEL2 == '1')
    //             Undefined()
    //         else if (AArch64.SCR_EL3.ST == '0')
    //             if (EL3SDDUndef())
    //                 Undefined()
    //             else
    //                 AArch64_SystemAccessTrap(EL3, 0x18)
    //         else
    //             CNTPS_CVAL_EL1 = X<t,0x40>;
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     CNTPS_CVAL_EL1 = X<t,0x40>;
}

// DBGBVR<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': (m)[0:3], 'op2': '100'})
//    if (   (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_BREAKPOINTS)
    //    || (IsFeatureImplemented(FEAT_Debugv8p9) && m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10 >= NUM_BREAKPOINTS))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.DBGBVRn_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGBVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGBVR_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGBVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGBVR_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGBVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGBVR_EL1<m> = X<t,0x40>;

// DBGBCR<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': (m)[0:3], 'op2': '101'})
//    if (   (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_BREAKPOINTS)
    //    || (IsFeatureImplemented(FEAT_Debugv8p9) && m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10 >= NUM_BREAKPOINTS))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.DBGBCRn_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGBCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGBCR_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGBCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGBCR_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGBCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGBCR_EL1<m> = X<t,0x40>;

// DBGWVR<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': (m)[0:3], 'op2': '110'})
//    if (   (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_WATCHPOINTS)
    //    || (IsFeatureImplemented(FEAT_Debugv8p9) && m + UInt(AArch64.MDSELR_EL1.BANK) * 0x10 >= NUM_WATCHPOINTS))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.DBGWVRn_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGWVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGWVR_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGWVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGWVR_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGWVR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGWVR_EL1<m> = X<t,0x40>;

// DBGWCR<m>_EL1
// encoding=OrderedDict({'op0': '10', 'op1': '000', 'CRn': '0000', 'CRm': (m)[0:3], 'op2': '111'})
//    if (   (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_WATCHPOINTS)
    //    || (IsFeatureImplemented(FEAT_Debugv8p9) && m + UInt(AArch64.MDSELR_EL1.BANK) * 0x10 >= NUM_WATCHPOINTS))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.DBGWCRn_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && (AArch64.MDCR_EL2.TDE):(AArch64.MDCR_EL2.TDA) != '00')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGWCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGWCR_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TDA == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TDA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGWCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGWCR_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR.TDA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else if (IsFeatureImplemented(FEAT_Debugv8p9))
//            DBGWCR_EL1<m + UInt(EffectiveMDSELR_EL1_BANK()) * 0x10> = X<t,0x40>;
//        else
//            DBGWCR_EL1<m> = X<t,0x40>;

// TRCIMSPEC<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '0', 'op2': '111'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRCIMSPECn == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCIMSPEC<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCIMSPEC<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCIMSPEC<m> = X<t,0x40>;

// TRCSEQEVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '00', 'op2': '100'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSEQEVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSEQEVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSEQEVR<m> = X<t,0x40>;

// TRCCNTRLDVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '00', 'op2': '101'})
//    if (m >= NUM_TRACE_COUNTERS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCNTRLDVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCNTRLDVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCNTRLDVR<m> = X<t,0x40>;

// TRCCNTCTLR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '01', 'op2': '101'})
//    if (m >= NUM_TRACE_COUNTERS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCNTCTLR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCNTCTLR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCNTCTLR<m> = X<t,0x40>;

// TRCEXTINSELR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '10', 'op2': '100'})
//    if (m >= NUM_TRACE_EXTERNAL_INPUT_SELECTOR_RESOURCES)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCEXTINSELR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCEXTINSELR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCEXTINSELR<m> = X<t,0x40>;

// TRCCNTVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0000', 'CRm': '10', 'op2': '101'})
//    if (m >= NUM_TRACE_COUNTERS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRCCNTVRn == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCNTVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCNTVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCNTVR<m> = X<t,0x40>;

// TRCSSCCR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0001', 'CRm': '0', 'op2': '010'})
//    if (m >= NUM_TRACE_SINGLE_SHOT_COMPARATOR_CONTROLS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSSCCR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSSCCR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSSCCR<m> = X<t,0x40>;

// TRCSSPCICR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0001', 'CRm': '0', 'op2': '011'})
//    if (m >= NUM_TRACE_SINGLE_SHOT_COMPARATOR_CONTROLS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSSPCICR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSSPCICR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSSPCICR<m> = X<t,0x40>;

// TRCSSCSR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0001', 'CRm': '1', 'op2': '010'})
//    if (m >= NUM_TRACE_SINGLE_SHOT_COMPARATOR_CONTROLS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRCSSCSRn == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSSCSR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSSCSR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCSSCSR<m> = X<t,0x40>;

// TRCRSCTLR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0001', 'CRm': (m)[0:3], 'op2': '00'})
//    if (m >= NUM_TRACE_RESOURCE_SELECTOR_PAIRS * 2)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCRSCTLR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCRSCTLR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCRSCTLR<m> = X<t,0x40>;

// TRCACVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0010', 'CRm': '0', 'op2': '00'})
//    if (m >= NUM_TRACE_ADDRESS_COMPARATOR_PAIRS * 2)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCACVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCACVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCACVR<m> = X<t,0x40>;

// TRCACATR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0010', 'CRm': '0', 'op2': '01'})
//    if (m >= NUM_TRACE_ADDRESS_COMPARATOR_PAIRS * 2)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCACATR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCACATR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCACATR<m> = X<t,0x40>;

// TRCCIDCVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0', 'op2': '000'})
//    if (m >= NUM_TRACE_CONTEXT_IDENTIFIER_COMPARATORS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCIDCVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCIDCVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCCIDCVR<m> = X<t,0x40>;

// TRCVMIDCVR<m>
// encoding=OrderedDict({'op0': '10', 'op1': '001', 'CRn': '0011', 'CRm': '0', 'op2': '001'})
//    if (m >= NUM_TRACE_VIRTUAL_CONTEXT_IDENTIFIER_COMPARATORS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPACR_EL1.TTA == '1')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.TRC == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCVMIDCVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TTA == '1')
//            Undefined()
//        else if (AArch64.CPTR_EL2.TTA == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TTA == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCVMIDCVR<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.CPTR_EL3.TTA == '1')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (IsFeatureImplemented(FEAT_TRBE_EXT) && AArch64.OSLSR_EL1.OSLK == '0' && HaltingAllowed() && ext.EDSCR2.TTA == '1')
//            Halt(DebugHalt_SoftwareAccess)
//        else
//            TRCVMIDCVR<m> = X<t,0x40>;

// SPMEVCNTR<m>_EL0
// encoding=OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1110', 'CRm': '000', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_SPMU))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (AArch64.MDSCR_EL1.EnSPM == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   !ELIsInHost(EL0)
         //        &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMEVCNTRn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVCNTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMEVCNTRn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVCNTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVCNTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        SPMEVCNTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;

// SPMEVTYPER<m>_EL0
// encoding=OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1110', 'CRm': '001', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_SPMU))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (AArch64.MDSCR_EL1.EnSPM == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   !ELIsInHost(EL0)
         //        &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVTYPER_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVTYPER_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVTYPER_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        SPMEVTYPER_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;

// SPMEVFILTR<m>_EL0
// encoding=OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1110', 'CRm': '010', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_SPMU))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (AArch64.MDSCR_EL1.EnSPM == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   !ELIsInHost(EL0)
         //        &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVFILTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVFILTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVFILTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        SPMEVFILTR_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;

// SPMEVFILT2R<m>_EL0
// encoding=OrderedDict({'op0': '10', 'op1': '011', 'CRn': '1110', 'CRm': '011', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_SPMU))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (AArch64.MDSCR_EL1.EnSPM == '0')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   !ELIsInHost(EL0)
         //        &&    (AArch64.SPMACCESSR_EL1)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVFILT2R_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HDFGWTR2_EL2.nSPMEVTYPERn_EL0 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.EnSPM == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (   EL2Enabled()
         //        &&    (AArch64.SPMACCESSR_EL2)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVFILT2R_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.EnPM2 == '0')
//            Undefined()
//        else if (   HaveEL(EL3)
         //        && EL3SDDUndefPriority()
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.EnPM2 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   HaveEL(EL3)
         //        &&    (AArch64.SPMACCESSR_EL3)<[UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2 + 2 - 1:UInt(AArch64.SPMSELR_EL0.SYSPMUSEL) * 2]>
         //           != '11')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        else
//            SPMEVFILT2R_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (!IsSPMUCounterImplemented(UInt(SPMSELR_EL0.SYSPMUSEL), UInt(SPMSELR_EL0.BANK) * 0x10 + m))
//            return;
//        SPMEVFILT2R_EL0<UInt(SPMSELR_EL0.SYSPMUSEL),UInt(SPMSELR_EL0.BANK) * 0x10 + m> = X<t,0x40>;

// ICC_AP0R<m>_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1000', 'op2': '1'})
//    if (!IsFeatureImplemented(FEAT_GICv3))
//        Undefined()
//    else if (m == 1 && NUM_GIC_PRIORITY_BITS < 6)
//        Undefined()
//    else if ((m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
//            Undefined()
//        else if (AArch64.ICC_SRE_EL1.SRE == '0')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.HCR_EL2.FMO == '1')
//            ICV_AP0R_EL1<m> = X<t,0x40>;
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            ICC_AP0R_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.FIQ == '1')
//            Undefined()
//        else if (AArch64.ICC_SRE_EL2.SRE == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.FIQ == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            ICC_AP0R_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.ICC_SRE_EL3.SRE == '0')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            ICC_AP0R_EL1<m> = X<t,0x40>;

// ICC_AP1R<m>_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1100', 'CRm': '1001', 'op2': '0'})
//    if (!IsFeatureImplemented(FEAT_GICv3))
//        Undefined()
//    else if (m == 1 && NUM_GIC_PRIORITY_BITS < 6)
//        Undefined()
//    else if ((m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
//            Undefined()
//        else if (AArch64.ICC_SRE_EL1.SRE == '0')
//            AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (EL2Enabled() && AArch64.ICH_HCR_EL2.TALL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.HCR_EL2.IMO == '1')
//            ICV_AP1R_EL1<m> = X<t,0x40>;
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3))
//            if (AArch64.SCR_EL3.NS == '0')
//                ICC_AP1R_EL1_S<m> = X<t,0x40>;
//            else
//                ICC_AP1R_EL1_NS<m> = X<t,0x40>;
//        else
//            ICC_AP1R_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.IRQ == '1')
//            Undefined()
//        else if (AArch64.ICC_SRE_EL2.SRE == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.IRQ == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3))
//            if (AArch64.SCR_EL3.NS == '0')
//                ICC_AP1R_EL1_S<m> = X<t,0x40>;
//            else
//                ICC_AP1R_EL1_NS<m> = X<t,0x40>;
//        else
//            ICC_AP1R_EL1<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.ICC_SRE_EL3.SRE == '0')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (AArch64.SCR_EL3.NS == '0')
//            ICC_AP1R_EL1_S<m> = X<t,0x40>;
//        else
//            ICC_AP1R_EL1_NS<m> = X<t,0x40>;

// AMEVCNTR0<m>_EL0
// encoding=OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '010', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_AMUv1))
//        Undefined()
//    else if (m >= 4)
//        Undefined()
//    else if (IsHighestEL(PSTATE.EL))
//        AMEVCNTR0_EL0<m> = X<t,0x40>;
//    else
//        Undefined()

// AMEVCNTR1<m>_EL0
// encoding=OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '110', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_AMUv1))
//        Undefined()
//    else if (m >= NUM_AMU_CG1_MONITORS)
//        Undefined()
//    else if (!IsG1ActivityMonitorImplemented(m))
//        Undefined()
//    else if (IsHighestEL(PSTATE.EL))
//        AMEVCNTR1_EL0<m> = X<t,0x40>;
//    else
//        Undefined()

// AMEVTYPER1<m>_EL0
// encoding=OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1101', 'CRm': '111', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_AMUv1))
//        Undefined()
//    else if (m >= NUM_AMU_CG1_MONITORS)
//        Undefined()
//    else if (!IsG1ActivityMonitorImplemented(m))
//        Undefined()
//    else if (IsHighestEL(PSTATE.EL) && !ImpDefBool("AArch64-AMEVCNTR1_EL0[m] is fixed"))
//        AMEVTYPER1_EL0<m> = X<t,0x40>;
//    else
//        Undefined()

// PMEVCNTR<m>_EL0
// encoding=OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '10', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_PMUv3))
//        Undefined()
//    else if (m >= GetNumEventCountersSelfHosted())
//        if (IsFeatureImplemented(FEAT_FGT))
//            Undefined()
//        else
//            ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.PMEVCNTRn_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && m >= GetNumEventCountersAccessible())
//            if (!IsFeatureImplemented(FEAT_FGT))
//                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//            else
//                AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   IsFeatureImplemented(FEAT_PMUv3p9)
         //        && PMUSERENR_EL0.UEN == '1'
         //        && ((AArch64.PMUACR_EL1)<m> == '0' || AArch64.PMUSERENR_EL0.ER == '1'))
//            return;
//        else
//            PMEVCNTR_EL0<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.PMEVCNTRn_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && m >= GetNumEventCountersAccessible())
//            if (!IsFeatureImplemented(FEAT_FGT))
//                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//            else
//                AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            PMEVCNTR_EL0<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            PMEVCNTR_EL0<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        PMEVCNTR_EL0<m> = X<t,0x40>;

// PMEVTYPER<m>_EL0
// encoding=OrderedDict({'op0': '11', 'op1': '011', 'CRn': '1110', 'CRm': '11', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_PMUv3))
//        Undefined()
//    else if (m >= GetNumEventCountersSelfHosted())
//        if (IsFeatureImplemented(FEAT_FGT))
//            Undefined()
//        else
//            ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//    else if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (AArch64.PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || AArch64.PMUSERENR_EL0.UEN == '0'))
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (   EL2Enabled()
         //        && !ELIsInHost(EL0)
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.PMEVTYPERn_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && m >= GetNumEventCountersAccessible())
//            if (!IsFeatureImplemented(FEAT_FGT))
//                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//            else
//                AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (   IsFeatureImplemented(FEAT_PMUv3p9)
         //        && PMUSERENR_EL0.UEN == '1'
         //        && ((AArch64.PMUACR_EL1)<m> == '0' || AArch64.PMUSERENR_EL0.ER == '1'))
//            return;
//        else
//            PMEVTYPER_EL0<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HDFGWTR_EL2.PMEVTYPERn_EL0 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && AArch64.MDCR_EL2.TPM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (EL2Enabled() && m >= GetNumEventCountersAccessible())
//            if (!IsFeatureImplemented(FEAT_FGT))
//                ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER)
//            else
//                AArch64_SystemAccessTrap(EL2, 0x18)
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            PMEVTYPER_EL0<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.TPM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.MDCR_EL3.TPM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            PMEVTYPER_EL0<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        PMEVTYPER_EL0<m> = X<t,0x40>;

// ICH_AP0R<m>_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1000', 'op2': '0'})
//    if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
//        Undefined()
//    else if (m == 1 && NUM_GIC_PREEMPTION_BITS < 6)
//        Undefined()
//    else if ((m == 2 || m == 3) && NUM_GIC_PREEMPTION_BITS < 7)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            NVMem<0x480 + 8 * m> = X<t,0x40>;
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (AArch64.ICC_SRE_EL2.SRE == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            ICH_AP0R_EL2<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.ICC_SRE_EL3.SRE == '0')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            ICH_AP0R_EL2<m> = X<t,0x40>;

// ICH_AP1R<m>_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '1001', 'op2': '0'})
//    if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
//        Undefined()
//    else if (m == 1 && NUM_GIC_PREEMPTION_BITS < 6)
//        Undefined()
//    else if ((m == 2 || m == 3) && NUM_GIC_PREEMPTION_BITS < 7)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            NVMem<0x4a0 + 8 * m> = X<t,0x40>;
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (AArch64.ICC_SRE_EL2.SRE == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            ICH_AP1R_EL2<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.ICC_SRE_EL3.SRE == '0')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            ICH_AP1R_EL2<m> = X<t,0x40>;

// ICH_LR<m>_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1100', 'CRm': '110', 'op2': (m)[0:2]})
//    if (!(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))))
//        Undefined()
//    else if (m >= NUM_GIC_LIST_REGS)
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            NVMem<0x400 + 8 * m> = X<t,0x40>;
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (AArch64.ICC_SRE_EL2.SRE == '0')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            ICH_LR_EL2<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        if (AArch64.ICC_SRE_EL3.SRE == '0')
//            AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            ICH_LR_EL2<m> = X<t,0x40>;

// AMEVCNTVOFF0<m>_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1101', 'CRm': '100', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_AMUv1p1))
//        Undefined()
//    else if (m >= 4)
//        Undefined()
//    else if (!(m IN (0, 2, 3)))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            NVMem<0xa00 + 8 * m> = X<t,0x40>;
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AMVOFFEN == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.AMVOFFEN == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            AMEVCNTVOFF0_EL2<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        AMEVCNTVOFF0_EL2<m> = X<t,0x40>;

// AMEVCNTVOFF1<m>_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '1101', 'CRm': '101', 'op2': (m)[0:2]})
//    if (!IsFeatureImplemented(FEAT_AMUv1p1))
//        Undefined()
//    else if (m >= NUM_AMU_CG1_MONITORS)
//        Undefined()
//    else if (!IsG1ActivityMonitorOffsetImplemented(m))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            NVMem<0xa80 + 8 * m> = X<t,0x40>;
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.CPTR_EL3.TAM == '1')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.AMVOFFEN == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.AMVOFFEN == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else if (HaveEL(EL3) && AArch64.CPTR_EL3.TAM == '1')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x18)
//        else
//            AMEVCNTVOFF1_EL2<m> = X<t,0x40>;
//    else if (PSTATE.EL == EL3)
//        AMEVCNTVOFF1_EL2<m> = X<t,0x40>;

// S3_<op1>_C<Cn>_C<Cm>_<op2>
// encoding=OrderedDict({'op0': '11', 'op1': op1[0:2], 'CRn': '1x11', 'CRm': Cm[0:3], 'op2': op2[0:2]})
//    if (PSTATE.EL == EL0)
//        if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.TIDCP == '1')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x18)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x18)
//        else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.TIDCP == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            AArch64_ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t)
//    else if (PSTATE.EL == EL1)
//        if (EL2Enabled() && AArch64.HCR_EL2.TIDCP == '1')
//            AArch64_SystemAccessTrap(EL2, 0x18)
//        else
//            AArch64_ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t)
//    else if (PSTATE.EL == EL2)
//        AArch64_ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t)
//    else if (PSTATE.EL == EL3)
//        AArch64_ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t)

/**
 * Implements the A64.MSRregister instruction (generic).
 *
 * @returns Strict VBox status code.
 * @param   pVCpu       The cross context virtual CPU structure of the
 *                      calling thread.
 * @param   idSysReg    The system register to write (IPRT format).
 * @param   idxGprSrc   The source GPR register number (for exceptions).
 * @param   uValue      The value to write.
 */
DECLHIDDEN(VBOXSTRICTRC) iemCImplA64_msr_generic(PVMCPU pVCpu, uint32_t idSysReg, uint32_t idxGprSrc, uint64_t uValue)
{
    Log(("iemCImplA64_msr(%#x, %#RX64)\n", idSysReg, uValue));
    uint32_t const uInstrEssence = IEM_CIMPL_SYSREG_INSTR_ESSENCE_MAKE(idSysReg, idxGprSrc, 0, 0xf);
    switch (idSysReg)
    {
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_OSDTRRX_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_OSDTRRX_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MDCCINT_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MDCCINT_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MDSCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MDSCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlags(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_OSDTRTX_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_OSDTRTX_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MDSELR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MDSELR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,5,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MDSTEPOP_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MDSTEPOP_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,0,6,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_OSECCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_OSECCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,0,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_OSLAR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_OSLAR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,3,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_OSDLR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_OSDLR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,1,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DBGPRCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_DBGPRCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,8,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DBGCLAIMSET_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_DBGCLAIMSET_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,7,9,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DBGCLAIMCLR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_DBGCLAIMCLR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,13,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMACCESSR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMACCESSR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,14,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMINTENSET_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMINTENSET_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,0,9,14,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMINTENCLR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMINTENCLR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCTRACEIDR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCTRACEIDR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCVICTLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCVICTLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCIMSPEC0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCIMSPEC0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCPRGCTLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCPRGCTLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCQCTLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCQCTLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCVIIECTLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCVIIECTLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,10,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCRSR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCRSR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,11,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCSTALLCTLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCSTALLCTLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,12,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCTSCTLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCTSCTLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,13,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCSYNCPR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCSYNCPR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,14,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCCCCTLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCCCCTLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,15,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCBBCTLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCBBCTLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCITEEDCR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCITEEDCR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCVISSCTLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCVISSCTLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCVIPCSSCTLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCVIPCSSCTLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCCONFIGR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCCONFIGR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCAUXCTLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCAUXCTLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,6,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCSEQRSTEVR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCSEQRSTEVR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,7,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCSEQSTR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCSEQSTR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,8,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCEVENTCTL0R(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCEVENTCTL0R(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,0,9,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCEVENTCTL1R(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCEVENTCTL1R(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCCIDCCTLR0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCCIDCCTLR0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCCIDCCTLR1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCCIDCCTLR1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCVMIDCCTLR0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCVMIDCCTLR0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,3,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCVMIDCCTLR1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCVMIDCCTLR1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,8,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCCLAIMSET(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCCLAIMSET(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,7,9,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCCLAIMCLR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCCLAIMCLR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_BRBCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_BRBCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_BRBFCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_BRBFCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_BRBTS_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_BRBTS_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_BRBINFINJ_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_BRBINFINJ_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_BRBSRCINJ_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_BRBSRCINJ_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,1,9,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_BRBTGTINJ_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_BRBTGTINJ_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,0,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DBGDTR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_DBGDTR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,0,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DBGDTRTX_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_DBGDTRTX_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMCR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMCR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMCNTENSET_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMCNTENSET_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMCNTENCLR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMCNTENCLR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMOVSCLR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMOVSCLR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMZR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMZR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,12,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMSELR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMSELR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,3,9,14,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMOVSSET_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMOVSSET_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,0,7,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DBGVCR32_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_DBGVCR32_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_BRBCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_BRBCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,4,9,13,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMACCESSR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMACCESSR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,5,9,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_BRBCR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_BRBCR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,5,9,13,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMACCESSR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPMACCESSR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,6,9,13,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMACCESSR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SPMACCESSR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,6,9,14,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMROOTCR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SPMROOTCR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(2,7,9,14,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPMSCR_EL1(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SPMSCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ACTLR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ACTLR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CPACR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CPACR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR2_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLR2_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_RGSR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_RGSR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_GCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ZCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ZCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRFCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRFCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCITECR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCITECR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SMPRI_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SMPRI_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SMCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SMCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLRMASK_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLRMASK_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ACTLRMASK_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ACTLRMASK_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CPACRMASK_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CPACRMASK_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR2MASK_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLR2MASK_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CPACRALIAS_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CPACRALIAS_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ACTLRALIAS_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ACTLRALIAS_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLRALIAS_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLRALIAS_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,1,4,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR2ALIAS_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLR2ALIAS_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MAIR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MAIR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MAIR2_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MAIR2_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PIRE0_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PIRE0_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PIR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PIR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_POR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_POR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_S2POR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_S2POR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMAIR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMAIR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMAIR2_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMAIR2_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_LORSA_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_LORSA_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_LOREA_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_LOREA_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_LORN_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_LORN_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_LORC_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_LORC_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAM1_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAM1_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAM0_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAM0_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMSM_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMSM_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMBW1_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMBW1_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMBW0_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMBW0_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,10,5,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMBWSM_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMBWSM_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VBAR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_VBAR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_RMR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_RMR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DISR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_DISR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_DIR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_DIR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_SGI1R_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_SGI1R_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_ASGI1R_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_ASGI1R_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,11,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_SGI0R_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_SGI0R_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_EOIR1_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_EOIR1_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_BPR1_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_BPR1_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_CTLR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_CTLR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_SRE_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_SRE_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_IGRPEN0_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_IGRPEN0_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,12,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_IGRPEN1_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_IGRPEN1_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_EOIR0_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_EOIR0_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,12,8,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_BPR0_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_BPR0_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CONTEXTIDR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CONTEXTIDR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_RCWSMASK_EL1(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_RCWSMASK_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TPIDR_EL1(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_TPIDR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ACCDATA_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ACCDATA_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_RCWMASK_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_RCWMASK_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,13,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCXTNUM_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCXTNUM_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,14,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTKCTL_EL1(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_CNTKCTL_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TTBR0_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TTBR0_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TTBR1_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TTBR1_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCR2_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCR2_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_APIAKeyLo_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_APIAKeyLo_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_APIAKeyHi_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_APIAKeyHi_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_APIBKeyLo_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_APIBKeyLo_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,1,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_APIBKeyHi_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_APIBKeyHi_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_APDAKeyLo_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_APDAKeyLo_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_APDAKeyHi_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_APDAKeyHi_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_APDBKeyLo_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_APDBKeyLo_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_APDBKeyHi_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_APDBKeyHi_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_APGAKeyLo_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_APGAKeyLo_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_APGAKeyHi_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_APGAKeyHi_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GCSCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_GCSCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GCSPR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_GCSPR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,5,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GCSCRE0_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_GCSCRE0_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCRMASK_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCRMASK_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCR2MASK_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCR2MASK_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCRALIAS_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCRALIAS_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,2,7,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCR2ALIAS_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCR2ALIAS_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPSR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPSR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ELR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ELR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SP_EL0(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SP_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPSel(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SPSel(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PAN(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_PAN(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_UAO(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_UAO(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ALLINT(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_ALLINT(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PM(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_PM(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,4,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_PMR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_PMR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AFSR0_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AFSR0_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AFSR1_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AFSR1_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ESR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ESR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ERRSELR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ERRSELR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ERXCTLR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ERXCTLR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ERXSTATUS_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ERXSTATUS_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ERXADDR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ERXADDR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ERXPFGCTL_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ERXPFGCTL_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,4,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ERXPFGCDN_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ERXPFGCDN_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ERXMISC0_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ERXMISC0_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ERXMISC1_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ERXMISC1_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ERXMISC2_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ERXMISC2_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,5,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ERXMISC3_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ERXMISC3_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TFSR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TFSR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,5,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TFSRE0_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TFSRE0_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,6,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_FAR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_FAR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,6,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PFAR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PFAR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,7,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PAR_EL1(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_PAR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMBLIMITR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMBLIMITR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMBPTR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMBPTR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMBSR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMBSR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSDSFR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSDSFR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,10,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMBMAR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMBMAR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRBLIMITR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRBLIMITR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRBPTR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRBPTR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRBBASER_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRBBASER_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRBSR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRBSR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRBMAR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRBMAR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRBMPAM_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRBMPAM_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,11,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRBTRG_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRBTRG_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,13,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSSCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSSCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMINTENSET_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMINTENSET_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMINTENCLR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMINTENCLR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMUACR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMUACR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMECR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMECR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,14,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMIAR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMIAR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSNEVFR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSNEVFR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSICR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSICR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSIRR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSIRR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSFCR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSFCR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSEVFR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSEVFR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,0,9,9,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSLATFR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSLATFR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,2,0,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CSSELR_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CSSELR_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,10,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_POR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_POR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TPIDR_EL0(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_TPIDR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TPIDRRO_EL0(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_TPIDRRO_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TPIDR2_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TPIDR2_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCXTNUM_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCXTNUM_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMCR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMCR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMUSERENR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMUSERENR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMCNTENCLR0_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMCNTENCLR0_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMCNTENSET0_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMCNTENSET0_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMCNTENCLR1_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMCNTENCLR1_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,13,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMCNTENSET1_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMCNTENSET1_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTFRQ_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTFRQ_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,15,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMCCFILTR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMCCFILTR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTP_TVAL_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTP_TVAL_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTP_CTL_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTP_CTL_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTP_CVAL_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTP_CVAL_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTV_TVAL_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTV_TVAL_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTV_CTL_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTV_CTL_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,14,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTV_CVAL_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTV_CVAL_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,2,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GCSPR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_GCSPR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_NZCV(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_NZCV(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DAIF(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_DAIF(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SVCR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SVCR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DIT(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_DIT(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SSBS(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SSBS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,2,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCO(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_TCO(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_FPCR(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_FPCR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_FPSR(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_FPSR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_FPMR(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_FPMR(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DSPSR_EL0(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_DSPSR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,4,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DLR_EL0(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_DLR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMCR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMCR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMCNTENSET_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMCNTENSET_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMCNTENCLR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMCNTENCLR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMOVSCLR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMOVSCLR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSWINC_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSWINC_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,12,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSELR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSELR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMCCNTR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMCCNTR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMXEVTYPER_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMXEVTYPER_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMXEVCNTR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMXEVCNTR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,13,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMZR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMZR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMUSERENR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMUSERENR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,14,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMOVSSET_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMOVSSET_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMICNTR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMICNTR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,3,9,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMICFILTR_EL0(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMICFILTR_EL0(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,0,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VPIDR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_VPIDR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,0,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VMPIDR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_VMPIDR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlagsAndPgmModeEl2(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ACTLR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ACTLR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR2_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLR2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlags(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MDCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MDCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CPTR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CPTR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HSTR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HSTR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HFGRTR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HFGRTR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HFGWTR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HFGWTR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HFGITR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HFGITR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,1,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HACR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HACR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ZCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ZCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRFCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRFCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HCRX_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HCRX_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlags(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCITECR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCITECR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SMPRIMAP_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SMPRIMAP_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SMCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SMCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SDER32_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SDER32_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLRMASK_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLRMASK_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ACTLRMASK_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ACTLRMASK_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CPTRMASK_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CPTRMASK_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,1,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR2MASK_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLR2MASK_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MAIR2_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MAIR2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MAIR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MAIR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PIRE0_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PIRE0_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PIR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PIR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_POR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_POR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_S2PIR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_S2PIR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMAIR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMAIR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMAIR2_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMAIR2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMHCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMHCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMVPMV_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMVPMV_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAM2_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAM2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMBW2_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMBW2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,5,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMBWCAP_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMBWCAP_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMVPM0_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMVPM0_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMVPM1_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMVPM1_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMVPM2_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMVPM2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMVPM3_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMVPM3_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMVPM4_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMVPM4_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMVPM5_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMVPM5_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMVPM6_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMVPM6_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,6,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMVPM7_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMVPM7_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,8,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MECID_P0_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_MECID_P0_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,8,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MECID_A0_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_MECID_A0_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,8,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MECID_P1_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_MECID_P1_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,8,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MECID_A1_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_MECID_A1_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,9,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VMECID_P_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_VMECID_P_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,10,9,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VMECID_A_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_VMECID_A_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VBAR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_VBAR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_RMR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_RMR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VDISR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_VDISR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICH_HCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICH_HCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,11,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICH_VMCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICH_VMCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,12,9,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_SRE_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ICC_SRE_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CONTEXTIDR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CONTEXTIDR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TPIDR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TPIDR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,13,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCXTNUM_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCXTNUM_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTVOFF_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTVOFF_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTPOFF_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTPOFF_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHCTL_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTHCTL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHP_TVAL_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTHP_TVAL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHP_CTL_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTHP_CTL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHP_CVAL_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTHP_CVAL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHV_TVAL_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTHV_TVAL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHV_CTL_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTHV_CTL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHV_CVAL_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTHV_CVAL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHVS_TVAL_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_CNTHVS_TVAL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHVS_CTL_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_CNTHVS_CTL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHVS_CVAL_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_CNTHVS_CVAL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHPS_TVAL_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_CNTHPS_TVAL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHPS_CTL_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_CNTHPS_CTL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,14,5,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTHPS_CVAL_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_CNTHPS_CVAL_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TTBR0_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TTBR0_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TTBR1_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TTBR1_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlagsAndPgmModeEl2(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCR2_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCR2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VTTBR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_VTTBR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VTCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_VTCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VNCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_VNCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HDBSSBR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HDBSSBR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HDBSSPROD_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HDBSSPROD_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HACDBSBR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HACDBSBR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HACDBSCONS_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HACDBSCONS_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GCSCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_GCSCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GCSPR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_GCSPR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VSTTBR_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_VSTTBR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,6,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VSTCR_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_VSTCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCRMASK_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCRMASK_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,2,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCR2MASK_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCR2MASK_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_DACR32_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_DACR32_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HDFGRTR2_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_HDFGRTR2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HDFGWTR2_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_HDFGWTR2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HFGRTR2_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_HFGRTR2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HFGWTR2_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_HFGWTR2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HDFGRTR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HDFGRTR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HDFGWTR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HDFGWTR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HAFGRTR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HAFGRTR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,3,1,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HFGITR2_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_HFGITR2_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPSR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPSR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ELR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ELR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SP_EL1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SP_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPSR_irq(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPSR_irq(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPSR_abt(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPSR_abt(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPSR_und(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPSR_und(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,4,3,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPSR_fiq(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPSR_fiq(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_IFSR32_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_IFSR32_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AFSR0_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AFSR0_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AFSR1_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AFSR1_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ESR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ESR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VSESR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_VSESR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_FPEXC32_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_FPEXC32_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,5,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TFSR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TFSR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,6,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_FAR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_FAR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,6,0,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_HPFAR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_HPFAR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,6,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PFAR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PFAR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,10,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMBSR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMBSR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,11,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRBSR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRBSR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,4,9,9,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSCR_EL2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSCR_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ACTLR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ACTLR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CPACR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CPACR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR2_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLR2_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ZCR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ZCR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRFCR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRFCR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRCITECR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRCITECR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SMCR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SMCR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLRMASK_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLRMASK_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ACTLRMASK_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ACTLRMASK_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CPACRMASK_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CPACRMASK_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,1,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR2MASK_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCTLR2MASK_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MAIR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MAIR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MAIR2_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MAIR2_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PIRE0_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PIRE0_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PIR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PIR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_POR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_POR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMAIR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMAIR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMAIR2_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AMAIR2_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAM1_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAM1_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,10,5,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMBW1_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_MPAMBW1_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,12,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VBAR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_VBAR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,13,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CONTEXTIDR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CONTEXTIDR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,13,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCXTNUM_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SCXTNUM_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTKCTL_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTKCTL_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTP_TVAL_EL02(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTP_TVAL_EL02(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTP_CTL_EL02(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTP_CTL_EL02(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTP_CVAL_EL02(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTP_CVAL_EL02(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTV_TVAL_EL02(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTV_TVAL_EL02(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTV_CTL_EL02(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTV_CTL_EL02(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,14,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTV_CVAL_EL02(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_CNTV_CVAL_EL02(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TTBR0_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TTBR0_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TTBR1_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TTBR1_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlagsAndPgmModeEl1(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCR2_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCR2_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GCSCR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_GCSCR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GCSPR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_GCSPR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,7,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCRMASK_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCRMASK_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,2,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCR2MASK_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TCR2MASK_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,4,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPSR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_SPSR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,4,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ELR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ELR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,5,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AFSR0_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AFSR0_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,5,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AFSR1_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_AFSR1_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,5,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ESR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_ESR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,5,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TFSR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TFSR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,6,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_FAR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_FAR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,6,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PFAR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PFAR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,9,10,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMBSR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMBSR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,9,11,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRBSR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_TRBSR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,5,9,9,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMSCR_EL12(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_msr_PMSCR_EL12(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SCTLR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlagsAndPgmModeEl3(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ACTLR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_ACTLR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,0,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCTLR2_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SCTLR2_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SCR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlags(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SDER32_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SDER32_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CPTR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_CPTR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_FGWTE3_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_FGWTE3_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ZCR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_ZCR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,2,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SMCR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SMCR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,1,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MDCR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_MDCR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MAIR2_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_MAIR2_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,10,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MECID_RL_A_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_MECID_RL_A_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MAIR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_MAIR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PIR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_PIR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_POR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_POR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMAIR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_AMAIR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AMAIR2_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_AMAIR2_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAM3_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_MPAM3_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,10,5,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MPAMBW3_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_MPAMBW3_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VBAR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_VBAR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_RMR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_RMR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VDISR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_VDISR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,12,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_CTLR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_ICC_CTLR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,12,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_SRE_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_ICC_SRE_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,12,12,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ICC_IGRPEN1_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_ICC_IGRPEN1_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,13,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TPIDR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_TPIDR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,13,0,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SCXTNUM_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SCXTNUM_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TTBR0_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_TTBR0_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TCR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_TCR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return iemCImplHlpRecalcFlagsAndPgmModeEl3(pVCpu, rcStrict);
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GPTBR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_GPTBR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GPCBW_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_GPCBW_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,1,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GPCCR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_GPCCR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GCSCR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_GCSCR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,2,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_GCSPR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_GCSPR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,4,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SPSR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SPSR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,4,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ELR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_ELR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,4,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_SP_EL2(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_SP_EL2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,5,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AFSR0_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_AFSR0_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,5,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_AFSR1_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_AFSR1_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,5,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_ESR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_ESR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,5,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_VSESR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_VSESR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,5,6,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TFSR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_TFSR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,6,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_FAR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_FAR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,6,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_MFAR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_MFAR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,9,10,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_PMBSR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_PMBSR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,6,9,11,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_TRBSR_EL3(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_TRBSR_EL3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,7,14,2,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTPS_TVAL_EL1(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_CNTPS_TVAL_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,7,14,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTPS_CTL_EL1(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_CNTPS_CTL_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(3,7,14,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_msr_CNTPS_CVAL_EL1(pVCpu, uValue);
            LogFlow(("iemCImplA64_msr_CNTPS_CVAL_EL1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
    }
    /* Fall back on handcoded handler. */
    return iemCImplA64_msr_fallback(pVCpu, idSysReg, idxGprSrc, uValue);
}

/**
 * Implements the A64.MSRregister instruction.
 *
 * @param   idSysReg    The system register to write (IPRT format).
 * @param   idxGprSrc   The source GPR register number (for exceptions).
 */
IEM_CIMPL_DEF_2(iemCImplA64_msr, uint32_t, idSysReg, uint32_t, idxGprSrc)
{
    uint64_t const uValue = idxGprSrc < ARMV8_A64_REG_XZR ? pVCpu->cpum.GstCtx.aGRegs[idxGprSrc].x : 0;
    return iemCImplA64_msr_generic(pVCpu, idSysReg, idxGprSrc, uValue);
}



/*
 * A64.MRRS
 *
 *   11 registers
 *    0 complete - 0 with unresolved registers
 *    0 incomplete
 */

// TTBR0_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HFGRTR_EL2.TTBR0_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.D128En == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (EffectiveHCR_EL2_NVx() IN ('111'))
//            (X<t2,0x40>,X<t,0x40>) = Split(NVMem<0x200,0x80>, 0x40);
//        else
//            (X<t2,0x40>,X<t,0x40>) = Split(TTBR0_EL1, 0x40);
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (ELIsInHost(EL2))
//            (X<t2,0x40>,X<t,0x40>) = Split(TTBR0_EL2, 0x40);
//        else
//            (X<t2,0x40>,X<t,0x40>) = Split(TTBR0_EL1, 0x40);
//    else if (PSTATE.EL == EL3)
//        (X<t2,0x40>,X<t,0x40>) = Split(TTBR0_EL1, 0x40);

// TTBR1_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (EL2Enabled() && AArch64.HCR_EL2.TRVM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HFGRTR_EL2.TTBR1_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.D128En == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (EffectiveHCR_EL2_NVx() IN ('111'))
//            (X<t2,0x40>,X<t,0x40>) = Split(NVMem<0x210,0x80>, 0x40);
//        else
//            (X<t2,0x40>,X<t,0x40>) = Split(TTBR1_EL1, 0x40);
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (ELIsInHost(EL2))
//            (X<t2,0x40>,X<t,0x40>) = Split(TTBR1_EL2, 0x40);
//        else
//            (X<t2,0x40>,X<t,0x40>) = Split(TTBR1_EL1, 0x40);
//    else if (PSTATE.EL == EL3)
//        (X<t2,0x40>,X<t,0x40>) = Split(TTBR1_EL1, 0x40);

// PAR_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0111', 'CRm': '0100', 'op2': '000'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HFGRTR_EL2.PAR_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.D128En == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (X<t2,0x40>,X<t,0x40>) = (PAR_EL1<[0x7f:0x40]>,PAR_EL1<[0x3f:0]>);
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (X<t2,0x40>,X<t,0x40>) = (PAR_EL1<[0x7f:0x40]>,PAR_EL1<[0x3f:0]>);
//    else if (PSTATE.EL == EL3)
//        (X<t2,0x40>,X<t,0x40>) = (PAR_EL1<[0x7f:0x40]>,PAR_EL1<[0x3f:0]>);

// RCWSMASK_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '011'})
//    if (!IsFeatureImplemented(FEAT_THE))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGRTR2_EL2.nRCWSMASK_EL1 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.D128En == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (X<t2,0x40>,X<t,0x40>) = (RCWSMASK_EL1<[0x7f:0x40]>,RCWSMASK_EL1<[0x3f:0]>);
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (X<t2,0x40>,X<t,0x40>) = (RCWSMASK_EL1<[0x7f:0x40]>,RCWSMASK_EL1<[0x3f:0]>);
//    else if (PSTATE.EL == EL3)
//        (X<t2,0x40>,X<t,0x40>) = (RCWSMASK_EL1<[0x7f:0x40]>,RCWSMASK_EL1<[0x3f:0]>);

// RCWMASK_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '110'})
//    if (!IsFeatureImplemented(FEAT_THE))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HFGRTR_EL2.nRCWMASK_EL1 == '0')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.D128En == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (X<t2,0x40>,X<t,0x40>) = (RCWMASK_EL1<[0x7f:0x40]>,RCWMASK_EL1<[0x3f:0]>);
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (X<t2,0x40>,X<t,0x40>) = (RCWMASK_EL1<[0x7f:0x40]>,RCWMASK_EL1<[0x3f:0]>);
//    else if (PSTATE.EL == EL3)
//        (X<t2,0x40>,X<t,0x40>) = (RCWMASK_EL1<[0x7f:0x40]>,RCWMASK_EL1<[0x3f:0]>);

// TTBR0_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (X<t2,0x40>,X<t,0x40>) = Split(TTBR0_EL2, 0x40);
//    else if (PSTATE.EL == EL3)
//        (X<t2,0x40>,X<t,0x40>) = Split(TTBR0_EL2, 0x40);

// TTBR1_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
//    if (!IsFeatureImplemented(FEAT_VHE))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (X<t2,0x40>,X<t,0x40>) = Split(TTBR1_EL2, 0x40);
//    else if (PSTATE.EL == EL3)
//        (X<t2,0x40>,X<t,0x40>) = Split(TTBR1_EL2, 0x40);

// VTTBR_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0001', 'op2': '000'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            (X<t2,0x40>,X<t,0x40>) = Split(NVMem<0x20,0x80>, 0x40);
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (X<t2,0x40>,X<t,0x40>) = Split(VTTBR_EL2, 0x40);
//    else if (PSTATE.EL == EL3)
//        (X<t2,0x40>,X<t,0x40>) = Split(VTTBR_EL2, 0x40);

// TTBR0_EL12
// encoding=OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() == '101')
//            (X<t2,0x40>,X<t,0x40>) = Split(NVMem<0x200,0x80>, 0x40);
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (ELIsInHost(EL2))
//            if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//                Undefined()
//            else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//                if (EL3SDDUndef())
//                    Undefined()
//                else
//                    AArch64_SystemAccessTrap(EL3, 0x14)
//            else
//                (X<t2,0x40>,X<t,0x40>) = Split(TTBR0_EL1, 0x40);
//        else
//            Undefined()
//    else if (PSTATE.EL == EL3)
//        if (ELIsInHost(EL2))
//            (X<t2,0x40>,X<t,0x40>) = Split(TTBR0_EL1, 0x40);
//        else
//            Undefined()

// TTBR1_EL12
// encoding=OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() == '101')
//            (X<t2,0x40>,X<t,0x40>) = Split(NVMem<0x210,0x80>, 0x40);
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (ELIsInHost(EL2))
//            if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//                Undefined()
//            else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//                if (EL3SDDUndef())
//                    Undefined()
//                else
//                    AArch64_SystemAccessTrap(EL3, 0x14)
//            else
//                (X<t2,0x40>,X<t,0x40>) = Split(TTBR1_EL1, 0x40);
//        else
//            Undefined()
//    else if (PSTATE.EL == EL3)
//        if (ELIsInHost(EL2))
//            (X<t2,0x40>,X<t,0x40>) = Split(TTBR1_EL1, 0x40);
//        else
//            Undefined()

// S3_<op1>_C<Cn>_C<Cm>_<op2>
// encoding=OrderedDict({'op0': '11', 'op1': op1[0:2], 'CRn': '1x11', 'CRm': Cm[0:3], 'op2': op2[0:2]})
//    if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnIDCP128 == '0')
//            Undefined()
//        else if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.TIDCP == '1')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x14)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x14)
//        else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.TIDCP == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (!ELIsInHost(EL0) && (!IsSCTLR2EL1Enabled() || AArch64.SCTLR2_EL1.EnIDCP128 == '0'))
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x14)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x14)
//        else if (ELIsInHost(EL0) && (!IsSCTLR2EL2Enabled() || AArch64.SCTLR2_EL2.EnIDCP128 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && !ELIsInHost(EL0) && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.EnIDCP128 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.EnIDCP128 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            AArch64_ImpDefSysRegRead128(op0, op1, CRn, CRm, op2, t, t2)
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnIDCP128 == '0')
//            Undefined()
//        else if (EL2Enabled() && AArch64.HCR_EL2.TIDCP == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.EnIDCP128 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.EnIDCP128 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            AArch64_ImpDefSysRegRead128(op0, op1, CRn, CRm, op2, t, t2)
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnIDCP128 == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.EnIDCP128 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            AArch64_ImpDefSysRegRead128(op0, op1, CRn, CRm, op2, t, t2)
//    else if (PSTATE.EL == EL3)
//        AArch64_ImpDefSysRegRead128(op0, op1, CRn, CRm, op2, t, t2)



/*
 * A64.MSRRregister
 *
 *   11 registers
 *    0 complete - 0 with unresolved registers
 *    0 incomplete
 */

// TTBR0_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HFGWTR_EL2.TTBR0_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.D128En == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (EffectiveHCR_EL2_NVx() IN ('111'))
//            NVMem<0x200,0x80> = (X<t2,0x40>):(X<t,0x40>);
//        else
//            TTBR0_EL1<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (ELIsInHost(EL2))
//            TTBR0_EL2<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//        else
//            TTBR0_EL1<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//    else if (PSTATE.EL == EL3)
//        TTBR0_EL1<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);

// TTBR1_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (EL2Enabled() && AArch64.HCR_EL2.TVM == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HFGWTR_EL2.TTBR1_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.D128En == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (EffectiveHCR_EL2_NVx() IN ('111'))
//            NVMem<0x210,0x80> = (X<t2,0x40>):(X<t,0x40>);
//        else
//            TTBR1_EL1<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (ELIsInHost(EL2))
//            TTBR1_EL2<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//        else
//            TTBR1_EL1<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//    else if (PSTATE.EL == EL3)
//        TTBR1_EL1<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);

// PAR_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '0111', 'CRm': '0100', 'op2': '000'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HFGWTR_EL2.PAR_EL1 == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.D128En == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (PAR_EL1<[0x7f:0x40]>,PAR_EL1<[0x3f:0]>) = (X<t2,0x40>,X<t,0x40>);
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (PAR_EL1<[0x7f:0x40]>,PAR_EL1<[0x3f:0]>) = (X<t2,0x40>,X<t,0x40>);
//    else if (PSTATE.EL == EL3)
//        (PAR_EL1<[0x7f:0x40]>,PAR_EL1<[0x3f:0]>) = (X<t2,0x40>,X<t,0x40>);

// RCWSMASK_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '011'})
//    if (!IsFeatureImplemented(FEAT_THE))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT2)
         //        && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGWTR2_EL2.nRCWSMASK_EL1 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.D128En == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (RCWSMASK_EL1<[0x7f:0x40]>,RCWSMASK_EL1<[0x3f:0]>) = (X<t2,0x40>,X<t,0x40>);
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (RCWSMASK_EL1<[0x7f:0x40]>,RCWSMASK_EL1<[0x3f:0]>) = (X<t2,0x40>,X<t,0x40>);
//    else if (PSTATE.EL == EL3)
//        (RCWSMASK_EL1<[0x7f:0x40]>,RCWSMASK_EL1<[0x3f:0]>) = (X<t2,0x40>,X<t,0x40>);

// RCWMASK_EL1
// encoding=OrderedDict({'op0': '11', 'op1': '000', 'CRn': '1101', 'CRm': '0000', 'op2': '110'})
//    if (!IsFeatureImplemented(FEAT_THE))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (   EL2Enabled()
         //        && IsFeatureImplemented(FEAT_FGT)
         //        && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
         //        && AArch64.HFGWTR_EL2.nRCWMASK_EL1 == '0')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.D128En == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (RCWMASK_EL1<[0x7f:0x40]>,RCWMASK_EL1<[0x3f:0]>) = (X<t2,0x40>,X<t,0x40>);
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.RCWMASKEn == '0')
//            Undefined()
//        else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.RCWMASKEn == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            (RCWMASK_EL1<[0x7f:0x40]>,RCWMASK_EL1<[0x3f:0]>) = (X<t2,0x40>,X<t,0x40>);
//    else if (PSTATE.EL == EL3)
//        (RCWMASK_EL1<[0x7f:0x40]>,RCWMASK_EL1<[0x3f:0]>) = (X<t2,0x40>,X<t,0x40>);

// TTBR0_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            TTBR0_EL2<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//    else if (PSTATE.EL == EL3)
//        TTBR0_EL2<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);

// TTBR1_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
//    if (!IsFeatureImplemented(FEAT_VHE))
//        Undefined()
//    else if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            TTBR1_EL2<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//    else if (PSTATE.EL == EL3)
//        TTBR1_EL2<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);

// VTTBR_EL2
// encoding=OrderedDict({'op0': '11', 'op1': '100', 'CRn': '0010', 'CRm': '0001', 'op2': '000'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() IN ('1x1'))
//            NVMem<0x20,0x80> = (X<t2,0x40>):(X<t,0x40>);
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            VTTBR_EL2<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//    else if (PSTATE.EL == EL3)
//        VTTBR_EL2<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);

// TTBR0_EL12
// encoding=OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '000'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() == '101')
//            NVMem<0x200,0x80> = (X<t2,0x40>):(X<t,0x40>);
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (ELIsInHost(EL2))
//            if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//                Undefined()
//            else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//                if (EL3SDDUndef())
//                    Undefined()
//                else
//                    AArch64_SystemAccessTrap(EL3, 0x14)
//            else
//                TTBR0_EL1<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//        else
//            Undefined()
//    else if (PSTATE.EL == EL3)
//        if (ELIsInHost(EL2))
//            TTBR0_EL1<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//        else
//            Undefined()

// TTBR1_EL12
// encoding=OrderedDict({'op0': '11', 'op1': '101', 'CRn': '0010', 'CRm': '0000', 'op2': '001'})
//    if (PSTATE.EL == EL0)
//        Undefined()
//    else if (PSTATE.EL == EL1)
//        if (EffectiveHCR_EL2_NVx() == '101')
//            NVMem<0x210,0x80> = (X<t2,0x40>):(X<t,0x40>);
//        else if (EffectiveHCR_EL2_NVx() IN ('xx1'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else
//            Undefined()
//    else if (PSTATE.EL == EL2)
//        if (ELIsInHost(EL2))
//            if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.D128En == '0')
//                Undefined()
//            else if (HaveEL(EL3) && AArch64.SCR_EL3.D128En == '0')
//                if (EL3SDDUndef())
//                    Undefined()
//                else
//                    AArch64_SystemAccessTrap(EL3, 0x14)
//            else
//                TTBR1_EL1<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//        else
//            Undefined()
//    else if (PSTATE.EL == EL3)
//        if (ELIsInHost(EL2))
//            TTBR1_EL1<[0x7f:0]> = (X<t2,0x40>):(X<t,0x40>);
//        else
//            Undefined()

// S3_<op1>_C<Cn>_C<Cm>_<op2>
// encoding=OrderedDict({'op0': '11', 'op1': op1[0:2], 'CRn': '1x11', 'CRm': Cm[0:3], 'op2': op2[0:2]})
//    if (PSTATE.EL == EL0)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnIDCP128 == '0')
//            Undefined()
//        else if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.TIDCP == '1')
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x14)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x14)
//        else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.TIDCP == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (!ELIsInHost(EL0) && (!IsSCTLR2EL1Enabled() || AArch64.SCTLR2_EL1.EnIDCP128 == '0'))
//            if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
//                AArch64_SystemAccessTrap(EL2, 0x14)
//            else
//                AArch64_SystemAccessTrap(EL1, 0x14)
//        else if (ELIsInHost(EL0) && (!IsSCTLR2EL2Enabled() || AArch64.SCTLR2_EL2.EnIDCP128 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && !ELIsInHost(EL0) && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.EnIDCP128 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.EnIDCP128 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            AArch64_ImpDefSysRegWrite128(op0, op1, CRn, CRm, op2, t, t2)
//    else if (PSTATE.EL == EL1)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnIDCP128 == '0')
//            Undefined()
//        else if (EL2Enabled() && AArch64.HCR_EL2.TIDCP == '1')
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (EL2Enabled() && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.EnIDCP128 == '0'))
//            AArch64_SystemAccessTrap(EL2, 0x14)
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.EnIDCP128 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            AArch64_ImpDefSysRegWrite128(op0, op1, CRn, CRm, op2, t, t2)
//    else if (PSTATE.EL == EL2)
//        if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.SCR_EL3.EnIDCP128 == '0')
//            Undefined()
//        else if (HaveEL(EL3) && AArch64.SCR_EL3.EnIDCP128 == '0')
//            if (EL3SDDUndef())
//                Undefined()
//            else
//                AArch64_SystemAccessTrap(EL3, 0x14)
//        else
//            AArch64_ImpDefSysRegWrite128(op0, op1, CRn, CRm, op2, t, t2)
//    else if (PSTATE.EL == EL3)
//        AArch64_ImpDefSysRegWrite128(op0, op1, CRn, CRm, op2, t, t2)



/*
 * A64.SYS
 *
 *  237 registers
 *  237 complete - 0 with unresolved registers
 *    0 incomplete
 */


/**
 * A64.IC IALLUIS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_IC_IALLUIS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(24)/*TPU*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(50)/*TICAB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysIc(pVCpu, kIemCImplA64CacheOpScope_AllUIS);
    }
    return iemCImplHlpA64SysIc(pVCpu, kIemCImplA64CacheOpScope_AllUIS);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TICAB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.ICIALLUIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_IC(CacheOpScope_ALLUIS)
    // else if (PSTATE.EL == EL2)
    //     AArch64_IC(CacheOpScope_ALLUIS)
    // else if (PSTATE.EL == EL3)
    //     AArch64_IC(CacheOpScope_ALLUIS)
}


/**
 * A64.DC CSW - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CSW(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(22)/*TSW*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_SetWay);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_SetWay);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_SetWay)
}


/**
 * A64.DC CGSW - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CGSW(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(22)/*TSW*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_SetWay);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Tag,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_SetWay);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_SetWay)
}


/**
 * A64.DC CGDSW - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1010', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CGDSW(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(22)/*TSW*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_SetWay);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_DataTag,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_SetWay);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_SetWay)
}


/**
 * A64.DC CISW - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1110', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CISW(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(22)/*TSW*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_SetWay);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_CleanInvalidate,
                               kIemCImplA64CacheOpScope_SetWay);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCISW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_SetWay)
}


/**
 * A64.DC CIGSW - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1110', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIGSW(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(22)/*TSW*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_SetWay);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Tag,
                               kIemCImplA64CacheOp_CleanInvalidate,
                               kIemCImplA64CacheOpScope_SetWay);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCISW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_CleanInvalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_CleanInvalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_CleanInvalidate, CacheOpScope_SetWay)
}


/**
 * A64.DC CIGDSW - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1110', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIGDSW(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(22)/*TSW*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_SetWay);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_DataTag,
                               kIemCImplA64CacheOp_CleanInvalidate,
                               kIemCImplA64CacheOpScope_SetWay);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCISW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_SetWay)
}


/**
 * A64.DC CIVAPS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIVAPS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPoPs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_PoPS);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_CleanInvalidate,
                               kIemCImplA64CacheOpScope_PoPS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PoPS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGITR2_EL2.nDCCIVAPS == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoPS)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoPS)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoPS)
}


/**
 * A64.DC CIGDVAPS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIGDVAPS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPoPs || !pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_PoPS);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_DataTag,
                               kIemCImplA64CacheOp_CleanInvalidate,
                               kIemCImplA64CacheOpScope_PoPS);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_PoPS) && IsFeatureImplemented(FEAT_MTE2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT2)
    //              && ((HaveEL(EL3) && AArch64.SCR_EL3.FGTEn2 == '0') || AArch64.HFGITR2_EL2.nDCCIVAPS == '0'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoPS)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoPS)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoPS)
}


/**
 * A64.IC IALLU - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '0101', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_IC_IALLU(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(24)/*TPU*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(52)/*TOCU*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64SysIc(pVCpu, kIemCImplA64CacheOpScope_AllUIS);
        return iemCImplHlpA64SysIc(pVCpu, kIemCImplA64CacheOpScope_AllU);
    }
    return iemCImplHlpA64SysIc(pVCpu, kIemCImplA64CacheOpScope_AllU);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TOCU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.ICIALLU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_IC(CacheOpScope_ALLUIS)
    //     else
    //         AArch64_IC(CacheOpScope_ALLU)
    // else if (PSTATE.EL == EL2)
    //     AArch64_IC(CacheOpScope_ALLU)
    // else if (PSTATE.EL == EL3)
    //     AArch64_IC(CacheOpScope_ALLU)
}


/**
 * A64.DC IVAC - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_IVAC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Invalidate,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_Invalidate,
                               kIemCImplA64CacheOpScope_PoC);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Invalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Invalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Invalidate, CacheOpScope_PoC)
}


/**
 * A64.DC ISW - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '0110', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_ISW(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(22)/*TSW*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Invalidate,
                                   kIemCImplA64CacheOpScope_SetWay);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_Invalidate,
                               kIemCImplA64CacheOpScope_SetWay);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCISW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Invalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Invalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Invalidate, CacheOpScope_SetWay)
}


/**
 * A64.DC IGVAC - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '0110', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_IGVAC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_Invalidate,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Tag,
                               kIemCImplA64CacheOp_Invalidate,
                               kIemCImplA64CacheOpScope_PoC);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Invalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Invalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Invalidate, CacheOpScope_PoC)
}


/**
 * A64.DC IGSW - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '0110', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_IGSW(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(22)/*TSW*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_Invalidate,
                                   kIemCImplA64CacheOpScope_SetWay);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Tag,
                               kIemCImplA64CacheOp_Invalidate,
                               kIemCImplA64CacheOpScope_SetWay);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCISW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Invalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Invalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Invalidate, CacheOpScope_SetWay)
}


/**
 * A64.DC IGDVAC - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_IGDVAC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_Invalidate,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_DataTag,
                               kIemCImplA64CacheOp_Invalidate,
                               kIemCImplA64CacheOpScope_PoC);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Invalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Invalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Invalidate, CacheOpScope_PoC)
}


/**
 * A64.DC IGDSW - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '0110', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_IGDSW(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(22)/*TSW*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_Invalidate,
                                   kIemCImplA64CacheOpScope_SetWay);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_DataTag,
                               kIemCImplA64CacheOp_Invalidate,
                               kIemCImplA64CacheOpScope_SetWay);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TSW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCISW == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Invalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Invalidate, CacheOpScope_SetWay)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Invalidate, CacheOpScope_SetWay)
}


/**
 * A64.GCSPUSHX  - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '0111', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_GCSPUSHX(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && !(pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/))
            return iemRaiseExlockException(pVCpu);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemCImplHlpIsGcsEnabled(pVCpu, 1))
            return iemCImplHlpA64GcsPushX(pVCpu);
    }
    else
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && !(pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/))
            return iemRaiseExlockException(pVCpu);
        if (iemCImplHlpIsGcsEnabled(pVCpu, 2))
            return iemCImplHlpA64GcsPushX(pVCpu);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '0')
    //         EXLOCKException()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.nGCSEPP == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (GCSEnabled(EL1))
    //         GCSPUSHX()
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '0')
    //         EXLOCKException()
    //     else if (GCSEnabled(EL2))
    //         GCSPUSHX()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '0')
    //         EXLOCKException()
    //     else if (GCSEnabled(EL3))
    //         GCSPUSHX()
}


/**
 * A64.GCSPOPCX  - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_GCSPOPCX(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/))
            return iemRaiseExlockException(pVCpu);
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemCImplHlpIsGcsEnabled(pVCpu, 1))
            return iemCImplHlpA64GcsPopCX(pVCpu);
    }
    else
    {
        if (   pGstFeats->fGcs
            && iemGetCurrentExlockEn(pVCpu, pGstFeats)
            && (pVCpu->cpum.GstCtx.fPState & UINT64_C(0x400000000)/*EXLOCK*/))
            return iemRaiseExlockException(pVCpu);
        if (iemCImplHlpIsGcsEnabled(pVCpu, 2))
            return iemCImplHlpA64GcsPopCX(pVCpu);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1')
    //         EXLOCKException()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.nGCSEPP == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (GCSEnabled(EL1))
    //         GCSPOPCX()
    // else if (PSTATE.EL == EL2)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1')
    //         EXLOCKException()
    //     else if (GCSEnabled(EL2))
    //         GCSPOPCX()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1')
    //         EXLOCKException()
    //     else if (GCSEnabled(EL3))
    //         GCSPOPCX()
}


/**
 * A64.GCSPOPX  - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '0111', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_GCSPOPX(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (iemCImplHlpIsGcsEnabled(pVCpu, 1))
            return iemCImplHlpA64GcsPopX(pVCpu);
    }
    else
    {
        if (iemCImplHlpIsGcsEnabled(pVCpu, 2))
            return iemCImplHlpA64GcsPopX(pVCpu);
    }
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (GCSEnabled(EL1))
    //         GCSPOPX()
    // else if (PSTATE.EL == EL2)
    //     if (GCSEnabled(EL2))
    //         GCSPOPX()
    // else if (PSTATE.EL == EL3)
    //     if (GCSEnabled(EL3))
    //         GCSPOPX()
}


/**
 * A64.AT S1E1R - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E1R(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(44)/*AT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_Read);
    }
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_Read);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.AT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.ATS1E1R == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Read)
    // else if (PSTATE.EL == EL2)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Read)
    // else if (PSTATE.EL == EL3)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Read)
}


/**
 * A64.AT S1E1W - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E1W(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(44)/*AT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_Write);
    }
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_Write);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.AT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.ATS1E1W == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Write)
    // else if (PSTATE.EL == EL2)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Write)
    // else if (PSTATE.EL == EL3)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Write)
}


/**
 * A64.AT S1E0R - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E0R(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(44)/*AT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 0, kIemCImplA64ATAccess_Read);
    }
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 0, kIemCImplA64ATAccess_Read);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.AT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.ATS1E0R == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Read)
    // else if (PSTATE.EL == EL2)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Read)
    // else if (PSTATE.EL == EL3)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Read)
}


/**
 * A64.AT S1E0W - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1000', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E0W(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(44)/*AT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 0, kIemCImplA64ATAccess_Write);
    }
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 0, kIemCImplA64ATAccess_Write);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.AT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.ATS1E0W == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Write)
    // else if (PSTATE.EL == EL2)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Write)
    // else if (PSTATE.EL == EL3)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Write)
}


/**
 * A64.AT S1E1RP - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E1RP(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPan2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(44)/*AT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_ReadPan);
    }
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_ReadPan);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAN2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.AT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.ATS1E1RP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_ReadPAN)
    // else if (PSTATE.EL == EL2)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_ReadPAN)
    // else if (PSTATE.EL == EL3)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_ReadPAN)
}


/**
 * A64.AT S1E1WP - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E1WP(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fPan2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(44)/*AT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_WritePan);
    }
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_WritePan);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_PAN2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.AT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.ATS1E1WP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_WritePAN)
    // else if (PSTATE.EL == EL2)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_WritePAN)
    // else if (PSTATE.EL == EL3)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_WritePAN)
}


/**
 * A64.AT S1E1A - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '0111', 'CRm': '1001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E1A(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fATs1a)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(44)/*AT*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_Any);
    }
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_Any);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_ATS1A))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.AT == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.ATS1E1A == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Any)
    // else if (PSTATE.EL == EL2)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Any)
    // else if (PSTATE.EL == EL3)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Any)
}


/**
 * A64.TLBI VMALLE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       uValue);
    return iemCImplHlpA64TlbiVmAll(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Osh,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVMALLE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Osh,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ASIDE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ASIDE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    return iemCImplHlpA64TlbiAsid(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIASIDE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAAE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAAE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VALE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Osh,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VAALE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0001', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAALE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAAE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAAE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI RVALE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAALE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0010', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAALE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI VMALLE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       uValue);
    return iemCImplHlpA64TlbiVmAll(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Ish,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVMALLE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Ish,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ASIDE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ASIDE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    return iemCImplHlpA64TlbiAsid(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIASIDE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAAE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAAE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VALE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Ish,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VAALE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0011', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAALE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAAE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAAE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI RVALE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAALE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0101', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAALE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI RVAE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiRva(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Any,
                                         kIemCImplA64TlbiMemAttr_AllAttr,
                                         uValue);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Any,
    //                              TLBI_ExcludeXS,
    //                              X<t,0x40>)
    //         else
    //             AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Any,
    //                              TLBI_AllAttr,
    //                              X<t,0x40>)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAAE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0110', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAAE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiRvaa(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Any,
                                          kIemCImplA64TlbiMemAttr_AllAttr,
                                          uValue);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Any,
    //                               TLBI_ExcludeXS,
    //                               X<t,0x40>)
    //         else
    //             AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Any,
    //                               TLBI_AllAttr,
    //                               X<t,0x40>)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI RVALE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiRva(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Last,
                                         kIemCImplA64TlbiMemAttr_AllAttr,
                                         uValue);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Last,
    //                              TLBI_ExcludeXS,
    //                              X<t,0x40>)
    //         else
    //             AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Last,
    //                              TLBI_AllAttr,
    //                              X<t,0x40>)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAALE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAALE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiRvaa(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Last,
                                          kIemCImplA64TlbiMemAttr_AllAttr,
                                          uValue);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Last,
    //                               TLBI_ExcludeXS,
    //                               X<t,0x40>)
    //         else
    //             AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Last,
    //                               TLBI_AllAttr,
    //                               X<t,0x40>)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI VMALLE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiVmAll(pVCpu,
                                           iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                           kIemCImplA64Regime_El10,
                                           iemCImplHlpGetCurrentVmId(pVCpu),
                                           kIemCImplA64Broadcast_ForcedIsh,
                                           kIemCImplA64TlbiMemAttr_AllAttr,
                                           uValue);
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       uValue);
    return iemCImplHlpA64TlbiVmAll(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Nsh,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVMALLE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBI_VMALL(SecurityStateAtEL(EL1),
    //                                Regime_EL10,
    //                                VMID<>,
    //                                Broadcast_ForcedISH,
    //                                TLBI_ExcludeXS,
    //                                X<t,0x40>)
    //         else
    //             AArch64_TLBI_VMALL(SecurityStateAtEL(EL1),
    //                                Regime_EL10,
    //                                VMID<>,
    //                                Broadcast_ForcedISH,
    //                                TLBI_AllAttr,
    //                                X<t,0x40>)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiVa(pVCpu,
                                        iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                        kIemCImplA64Regime_El10,
                                        iemCImplHlpGetCurrentVmId(pVCpu),
                                        kIemCImplA64Broadcast_ForcedIsh,
                                        kIemCImplA64TlbiLevel_Any,
                                        kIemCImplA64TlbiMemAttr_AllAttr,
                                        uValue);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Nsh,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                             Regime_EL10,
    //                             VMID<>,
    //                             Broadcast_ForcedISH,
    //                             TLBILevel_Any,
    //                             TLBI_ExcludeXS,
    //                             X<t,0x40>)
    //         else
    //             AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                             Regime_EL10,
    //                             VMID<>,
    //                             Broadcast_ForcedISH,
    //                             TLBILevel_Any,
    //                             TLBI_AllAttr,
    //                             X<t,0x40>)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ASIDE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0111', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ASIDE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiAsid(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiMemAttr_AllAttr,
                                          uValue);
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    return iemCImplHlpA64TlbiAsid(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIASIDE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBI_ASID(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBI_ExcludeXS,
    //                               X<t,0x40>)
    //         else
    //             AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ForcedISH, TLBI_AllAttr, X<t,0x40>)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAAE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAAE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiVaa(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Any,
                                         kIemCImplA64TlbiMemAttr_AllAttr,
                                         uValue);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Any,
    //                              TLBI_ExcludeXS,
    //                              X<t,0x40>)
    //         else
    //             AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Any,
    //                              TLBI_AllAttr,
    //                              X<t,0x40>)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VALE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiVa(pVCpu,
                                        iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                        kIemCImplA64Regime_El10,
                                        iemCImplHlpGetCurrentVmId(pVCpu),
                                        kIemCImplA64Broadcast_ForcedIsh,
                                        kIemCImplA64TlbiLevel_Last,
                                        kIemCImplA64TlbiMemAttr_AllAttr,
                                        uValue);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Nsh,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                             Regime_EL10,
    //                             VMID<>,
    //                             Broadcast_ForcedISH,
    //                             TLBILevel_Last,
    //                             TLBI_ExcludeXS,
    //                             X<t,0x40>)
    //         else
    //             AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                             Regime_EL10,
    //                             VMID<>,
    //                             Broadcast_ForcedISH,
    //                             TLBILevel_Last,
    //                             TLBI_AllAttr,
    //                             X<t,0x40>)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VAALE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0111', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAALE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiVaa(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Last,
                                         kIemCImplA64TlbiMemAttr_AllAttr,
                                         uValue);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Last,
    //                              TLBI_ExcludeXS,
    //                              X<t,0x40>)
    //         else
    //             AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Last,
    //                              TLBI_AllAttr,
    //                              X<t,0x40>)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VMALLE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       uValue);
    return iemCImplHlpA64TlbiVmAll(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Osh,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVMALLE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Osh,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ASIDE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ASIDE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    return iemCImplHlpA64TlbiAsid(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIASIDE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAAE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAAE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VALE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Osh,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VAALE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0001', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAALE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAAE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAAE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI RVALE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAALE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0010', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAALE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI VMALLE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       uValue);
    return iemCImplHlpA64TlbiVmAll(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Ish,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVMALLE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Ish,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ASIDE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0011', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ASIDE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    return iemCImplHlpA64TlbiAsid(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIASIDE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAAE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAAE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VALE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Ish,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VAALE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0011', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAALE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAAE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAAE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI RVALE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAALE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0101', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAALE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI RVAE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiRva(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Any,
                                         kIemCImplA64TlbiMemAttr_ExcludeXs,
                                         uValue);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ForcedISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAAE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0110', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAAE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiRvaa(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Any,
                                          kIemCImplA64TlbiMemAttr_ExcludeXs,
                                          uValue);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ForcedISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI RVALE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiRva(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Last,
                                         kIemCImplA64TlbiMemAttr_ExcludeXs,
                                         uValue);
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ForcedISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAALE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAALE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiRvaa(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Last,
                                          kIemCImplA64TlbiMemAttr_ExcludeXs,
                                          uValue);
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiRvaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    return iemCImplHlpA64TlbiRvaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ForcedISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_RVAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           X<t,0x40>)
}


/**
 * A64.TLBI VMALLE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiVmAll(pVCpu,
                                           iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                           kIemCImplA64Regime_El10,
                                           iemCImplHlpGetCurrentVmId(pVCpu),
                                           kIemCImplA64Broadcast_ForcedIsh,
                                           kIemCImplA64TlbiMemAttr_ExcludeXs,
                                           uValue);
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVmAll(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       uValue);
    return iemCImplHlpA64TlbiVmAll(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Nsh,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVMALLE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ForcedISH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiVa(pVCpu,
                                        iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                        kIemCImplA64Regime_El10,
                                        iemCImplHlpGetCurrentVmId(pVCpu),
                                        kIemCImplA64Broadcast_ForcedIsh,
                                        kIemCImplA64TlbiLevel_Any,
                                        kIemCImplA64TlbiMemAttr_ExcludeXs,
                                        uValue);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Nsh,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ForcedISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ASIDE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0111', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ASIDE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiAsid(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiMemAttr_ExcludeXs,
                                          uValue);
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiAsid(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    return iemCImplHlpA64TlbiAsid(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIASIDE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ForcedISH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAAE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAAE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiVaa(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Any,
                                         kIemCImplA64TlbiMemAttr_ExcludeXs,
                                         uValue);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ForcedISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VALE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiVa(pVCpu,
                                        iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                        kIemCImplA64Regime_El10,
                                        iemCImplHlpGetCurrentVmId(pVCpu),
                                        kIemCImplA64Broadcast_ForcedIsh,
                                        kIemCImplA64TlbiLevel_Last,
                                        kIemCImplA64TlbiMemAttr_ExcludeXs,
                                        uValue);
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                kIemCImplA64Regime_El10,
                                iemCImplHlpGetCurrentVmId(pVCpu),
                                kIemCImplA64Broadcast_Nsh,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ForcedISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VAALE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0111', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAALE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbiVaa(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Last,
                                         kIemCImplA64TlbiMemAttr_ExcludeXs,
                                         uValue);
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbiVaa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiVaa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ForcedISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VAA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.BRB IALL - OrderedDict({'op0': '01', 'op1': '001', 'CRn': '0111', 'CRm': '0010', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_BRB_IALL(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64BrbIAll(pVCpu);
    }
    return iemCImplHlpA64BrbIAll(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.nBRBIALL == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRB_IALL()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRB_IALL()
    // else if (PSTATE.EL == EL3)
    //     BRB_IALL()
}


/**
 * A64.BRB INJ - OrderedDict({'op0': '01', 'op1': '001', 'CRn': '0111', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_BRB_INJ(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fBrbe)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && pGstFeats->fFgt)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64BrbInj(pVCpu);
    }
    return iemCImplHlpA64BrbInj(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_BRBE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.nBRBINJ == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRB_INJ()
    // else if (PSTATE.EL == EL2)
    //     if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         Undefined()
    //     else if (HaveEL(EL3) && EL3SDDUndefPriority() && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         Undefined()
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE != '11' && AArch64.SCR_EL3.NS == '0')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (HaveEL(EL3) && AArch64.MDCR_EL3.SBRBE IN 'x0' && AArch64.SCR_EL3.NS == '1')
    //         if (EL3SDDUndef())
    //             Undefined()
    //         else
    //             AArch64_SystemAccessTrap(EL3, 0x18)
    //     else
    //         BRB_INJ()
    // else if (PSTATE.EL == EL3)
    //     BRB_INJ()
}


/**
 * A64.DC CVAC - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CVAC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_PoC);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoC)
}


/**
 * A64.DC CGVAC - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CGVAC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Tag,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_PoC);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoC)
}


/**
 * A64.DC CGDVAC - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CGDVAC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_DataTag,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_PoC);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC)
}


/**
 * A64.DC CVAOC - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CVAOC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fOccmo)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_OuterCache);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_OuterCache);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_OuterCache);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_OCCMO))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_OuterCache)
}


/**
 * A64.DC CVAU - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CVAU(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(24)/*TPU*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(52)/*TOCU*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoU);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(24)/*TPU*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(52)/*TOCU*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoU);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_PoU);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TOCU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoU)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TOCU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoU)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoU)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoU)
}


/**
 * A64.DC CGDVAOC - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1011', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CGDVAOC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fOccmo || !pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_OuterCache);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_OuterCache);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_DataTag,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_OuterCache);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_OCCMO) && IsFeatureImplemented(FEAT_MTE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_OuterCache)
}


/**
 * A64.DC CVAP - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CVAP(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fDpb)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoP);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoP);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_PoP);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_DPB))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoP)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoP)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoP)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoP)
}


/**
 * A64.DC CGVAP - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CGVAP(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoP);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoP);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Tag,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_PoP);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoP)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoP)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoP)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoP)
}


/**
 * A64.DC CGDVAP - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CGDVAP(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoP);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoP);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_DataTag,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_PoP);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoP)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVAP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoP)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoP)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoP)
}


/**
 * A64.DC CVADP - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CVADP(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fDpb2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoDP);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoDP);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_PoDP);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_DPB2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVADP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoDP)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVADP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoDP)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoDP)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_Clean, CacheOpScope_PoDP)
}


/**
 * A64.DC CGVADP - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CGVADP(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fDpb2 || !pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoDP);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoDP);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Tag,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_PoDP);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_DPB2) && IsFeatureImplemented(FEAT_MTE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVADP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoDP)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVADP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoDP)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoDP)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_Clean, CacheOpScope_PoDP)
}


/**
 * A64.DC CGDVADP - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CGDVADP(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fDpb2 || !pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoDP);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_Clean,
                                   kIemCImplA64CacheOpScope_PoDP);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_DataTag,
                               kIemCImplA64CacheOp_Clean,
                               kIemCImplA64CacheOpScope_PoDP);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_DPB2) && IsFeatureImplemented(FEAT_MTE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVADP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoDP)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCVADP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoDP)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoDP)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoDP)
}


/**
 * A64.DC CIVAC - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIVAC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_CleanInvalidate,
                               kIemCImplA64CacheOpScope_PoC);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC)
}


/**
 * A64.DC CIGVAC - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1110', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIGVAC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Tag,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Tag,
                               kIemCImplA64CacheOp_CleanInvalidate,
                               kIemCImplA64CacheOpScope_PoC);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC)
}


/**
 * A64.DC CIGDVAC - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIGDVAC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_PoC);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_DataTag,
                               kIemCImplA64CacheOp_CleanInvalidate,
                               kIemCImplA64CacheOpScope_PoC);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC)
}


/**
 * A64.DC CIVAOC - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIVAOC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fOccmo)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_OuterCache);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_Data,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_OuterCache);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_Data,
                               kIemCImplA64CacheOp_CleanInvalidate,
                               kIemCImplA64CacheOpScope_OuterCache);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_OCCMO))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_OuterCache)
}


/**
 * A64.DC CIGDVAOC - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '1111', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIGDVAOC(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fOccmo || !pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_OuterCache);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(23)/*TPCP*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysDc(pVCpu,
                                   uValue,
                                   kIemCImplA64CacheType_DataTag,
                                   kIemCImplA64CacheOp_CleanInvalidate,
                                   kIemCImplA64CacheOpScope_OuterCache);
    }
    return iemCImplHlpA64SysDc(pVCpu,
                               uValue,
                               kIemCImplA64CacheType_DataTag,
                               kIemCImplA64CacheOp_CleanInvalidate,
                               kIemCImplA64CacheOpScope_OuterCache);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_OCCMO) && IsFeatureImplemented(FEAT_MTE)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPCP == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCCIVAC == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL2)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_OuterCache)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_OuterCache)
}


/**
 * A64.TRCIT  - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0010', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TRCIT(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fIte)
        return iemRaiseUndefined(pVCpu);
    return iemCImplHlpA64TrcIt(pVCpu, uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_ITE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     AArch64_TRCIT(X<t,0x40>)
    // else if (PSTATE.EL == EL1)
    //     AArch64_TRCIT(X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     AArch64_TRCIT(X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     AArch64_TRCIT(X<t,0x40>)
}


/**
 * A64.CFP RCTX - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0011', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_CFP_RCTX(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpecres)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(10)/*EnRCTX*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(10)/*EnRCTX*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_ControlFlow);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_ControlFlow);
    }
    return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_ControlFlow);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPECRES))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.EnRCTX == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.CFPRCTX == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.EnRCTX == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_RestrictPrediction(X<t,0x40>, RestrictType_ControlFlow)
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.CFPRCTX == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_RestrictPrediction(X<t,0x40>, RestrictType_ControlFlow)
    // else if (PSTATE.EL == EL2)
    //     AArch64_RestrictPrediction(X<t,0x40>, RestrictType_ControlFlow)
    // else if (PSTATE.EL == EL3)
    //     AArch64_RestrictPrediction(X<t,0x40>, RestrictType_ControlFlow)
}


/**
 * A64.DVP RCTX - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DVP_RCTX(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpecres)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(10)/*EnRCTX*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(10)/*EnRCTX*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_DataValue);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_DataValue);
    }
    return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_DataValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPECRES))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.EnRCTX == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DVPRCTX == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.EnRCTX == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_RestrictPrediction(X<t,0x40>, RestrictType_DataValue)
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DVPRCTX == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_RestrictPrediction(X<t,0x40>, RestrictType_DataValue)
    // else if (PSTATE.EL == EL2)
    //     AArch64_RestrictPrediction(X<t,0x40>, RestrictType_DataValue)
    // else if (PSTATE.EL == EL3)
    //     AArch64_RestrictPrediction(X<t,0x40>, RestrictType_DataValue)
}


/**
 * A64.COSP RCTX - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0011', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_COSP_RCTX(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpecres2)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(10)/*EnRCTX*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(10)/*EnRCTX*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_Other);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_Other);
    }
    return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_Other);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPECRES2))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.EnRCTX == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.COSPRCTX == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.EnRCTX == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_RestrictPrediction(X<t,0x40>, RestrictType_Other)
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.COSPRCTX == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_RestrictPrediction(X<t,0x40>, RestrictType_Other)
    // else if (PSTATE.EL == EL2)
    //     AArch64_RestrictPrediction(X<t,0x40>, RestrictType_Other)
    // else if (PSTATE.EL == EL3)
    //     AArch64_RestrictPrediction(X<t,0x40>, RestrictType_Other)
}


/**
 * A64.CPP RCTX - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0011', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_CPP_RCTX(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fSpecres)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(10)/*EnRCTX*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(10)/*EnRCTX*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_CachePrefetch);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_CachePrefetch);
    }
    return iemCImplHlpA64RestrictPrediction(pVCpu, uValue, kIemCImplA64RestrictType_CachePrefetch);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_SPECRES))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.EnRCTX == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.CPPRCTX == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.EnRCTX == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_RestrictPrediction(X<t,0x40>, RestrictType_CachePrefetch)
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.CPPRCTX == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_RestrictPrediction(X<t,0x40>, RestrictType_CachePrefetch)
    // else if (PSTATE.EL == EL2)
    //     AArch64_RestrictPrediction(X<t,0x40>, RestrictType_CachePrefetch)
    // else if (PSTATE.EL == EL3)
    //     AArch64_RestrictPrediction(X<t,0x40>, RestrictType_CachePrefetch)
}


/**
 * A64.DC ZVA - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_ZVA(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(14)/*DZE*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(28)/*TDZ*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(14)/*DZE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64MemZero(pVCpu, uValue, kIemCImplA64CacheType_Data);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(28)/*TDZ*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64MemZero(pVCpu, uValue, kIemCImplA64CacheType_Data);
    }
    return iemCImplHlpA64MemZero(pVCpu, uValue, kIemCImplA64CacheType_Data);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.DZE == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TDZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCZVA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.DZE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_MemZero(X<t,0x40>, CacheType_Data)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TDZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCZVA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_MemZero(X<t,0x40>, CacheType_Data)
    // else if (PSTATE.EL == EL2)
    //     AArch64_MemZero(X<t,0x40>, CacheType_Data)
    // else if (PSTATE.EL == EL3)
    //     AArch64_MemZero(X<t,0x40>, CacheType_Data)
}


/**
 * A64.DC GVA - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_GVA(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(14)/*DZE*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(28)/*TDZ*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(14)/*DZE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64MemZero(pVCpu, uValue, kIemCImplA64CacheType_Tag);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(28)/*TDZ*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64MemZero(pVCpu, uValue, kIemCImplA64CacheType_Tag);
    }
    return iemCImplHlpA64MemZero(pVCpu, uValue, kIemCImplA64CacheType_Tag);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.DZE == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TDZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCZVA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.DZE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_MemZero(X<t,0x40>, CacheType_Tag)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TDZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCZVA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_MemZero(X<t,0x40>, CacheType_Tag)
    // else if (PSTATE.EL == EL2)
    //     AArch64_MemZero(X<t,0x40>, CacheType_Tag)
    // else if (PSTATE.EL == EL3)
    //     AArch64_MemZero(X<t,0x40>, CacheType_Tag)
}


/**
 * A64.DC GZVA - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_GZVA(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fMte)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(14)/*DZE*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(28)/*TDZ*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(14)/*DZE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64MemZero(pVCpu, uValue, kIemCImplA64CacheType_DataTag);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(28)/*TDZ*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64MemZero(pVCpu, uValue, kIemCImplA64CacheType_DataTag);
    }
    return iemCImplHlpA64MemZero(pVCpu, uValue, kIemCImplA64CacheType_DataTag);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MTE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.DZE == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TDZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCZVA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.DZE == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_MemZero(X<t,0x40>, CacheType_Data_Tag)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TDZ == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.DCZVA == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_MemZero(X<t,0x40>, CacheType_Data_Tag)
    // else if (PSTATE.EL == EL2)
    //     AArch64_MemZero(X<t,0x40>, CacheType_Data_Tag)
    // else if (PSTATE.EL == EL3)
    //     AArch64_MemZero(X<t,0x40>, CacheType_Data_Tag)
}


/**
 * A64.IC IVAU - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_IC_IVAU(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (   (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && !(pVCpu->cpum.GstCtx.Sctlr.u64 & RT_BIT_32(26)/*UCI*/))
        {
            if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
                return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        }
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(24)/*TPU*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fEl2
            && (   !pGstFeats->fVhe
                || !pGstFeats->fEl2
                || (pGstFeats->fE2H0 && !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
                || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(52)/*TOCU*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/)
            && !(pVCpu->cpum.GstCtx.SctlrEl2.u64 & RT_BIT_32(26)/*UCI*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysIcWithArg(pVCpu, uValue, kIemCImplA64CacheOpScope_PoU);
    }
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(24)/*TPU*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(52)/*TOCU*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64SysIcWithArg(pVCpu, uValue, kIemCImplA64CacheOpScope_PoU);
    }
    return iemCImplHlpA64SysIcWithArg(pVCpu, uValue, kIemCImplA64CacheOpScope_PoU);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     if (!ELIsInHost(EL0) && AArch64.SCTLR_EL1.UCI == '0')
    //         if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1')
    //             AArch64_SystemAccessTrap(EL2, 0x18)
    //         else
    //             AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TPU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && !ELIsInHost(EL0) && AArch64.HCR_EL2.TOCU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && !ELIsInHost(EL0)
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.ICIVAU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (ELIsInHost(EL0) && AArch64.SCTLR_EL2.UCI == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_IC(X<t,0x40>, CacheOpScope_PoU)
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TPU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TOCU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.ICIVAU == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         AArch64_IC(X<t,0x40>, CacheOpScope_PoU)
    // else if (PSTATE.EL == EL2)
    //     AArch64_IC(X<t,0x40>, CacheOpScope_PoU)
    // else if (PSTATE.EL == EL3)
    //     AArch64_IC(X<t,0x40>, CacheOpScope_PoU)
}


/**
 * A64.GCSPUSHM  - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_GCSPUSHM(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
    {
        if (!pGstFeats->fEl2 || ((pVCpu->cpum.GstCtx.HcrEl2.u64 >> 27) & UINT32_C(1)/*TGE*/) != 1)
            return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        if (iemCImplHlpIsGcsEnabled(pVCpu, 0))
            return iemCImplHlpA64GcsPushM(pVCpu, uValue);
    }
    else if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
        return iemRaiseSystemAccessTrap(pVCpu, 1, uInstrEssence);
    else
        return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     if ((!EL2Enabled() || AArch64.HCR_EL2.TGE != '1') && AArch64.GCSCRE0_EL1.PUSHMEn == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TGE == '1' && AArch64.GCSCRE0_EL1.PUSHMEn == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (GCSEnabled(EL0))
    //         GCSPUSHM(X<t,0x40>)
    // else if (PSTATE.EL == EL1)
    //     if (AArch64.GCSCR_EL1.PUSHMEn == '0')
    //         AArch64_SystemAccessTrap(EL1, 0x18)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.nGCSPUSHM_EL1 == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (GCSEnabled(EL1))
    //         GCSPUSHM(X<t,0x40>)
    // else if (PSTATE.EL == EL2)
    //     if (AArch64.GCSCR_EL2.PUSHMEn == '0')
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else if (GCSEnabled(EL2))
    //         GCSPUSHM(X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (AArch64.GCSCR_EL3.PUSHMEn == '0')
    //         AArch64_SystemAccessTrap(EL3, 0x18)
    //     else if (GCSEnabled(EL3))
    //         GCSPUSHM(X<t,0x40>)
}


/**
 * A64.GCSSS1  - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0111', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_GCSSS1(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (iemCImplHlpIsGcsEnabledAtCurrentEl(pVCpu))
        return iemCImplHlpA64GcsSs1(pVCpu, uValue);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (GCSEnabled(PSTATE.EL))
    //     GCSSS1(X<t,0x40>)
}


/**
 * A64.DC CIPAE - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '0111', 'CRm': '1110', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIPAE(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_MEC))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoE)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoE)
}


/**
 * A64.DC CIGDPAE - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '0111', 'CRm': '1110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIGDPAE(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_MEC) && IsFeatureImplemented(FEAT_MTE2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (!IsCurrentSecurityState(SS_Realm))
    //         Undefined()
    //     else
    //         AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoE)
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoE)
}


/**
 * A64.AT S1E2R - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '0111', 'CRm': '1000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E2R(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 2, kIemCImplA64ATAccess_Read);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL2, ATAccess_Read)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL2, ATAccess_Read)
}


/**
 * A64.AT S1E2W - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '0111', 'CRm': '1000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E2W(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 2, kIemCImplA64ATAccess_Write);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL2, ATAccess_Write)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL2, ATAccess_Write)
}


/**
 * A64.AT S12E1R - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '0111', 'CRm': '1000', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S12E1R(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (   (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & UINT64_C(0x1001) /*DC,VM*/))
        return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_Read);
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_12, 1, kIemCImplA64ATAccess_Read);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0) || (AArch64.HCR_EL2.DC):(AArch64.HCR_EL2.VM) == '00')
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Read)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_12, EL1, ATAccess_Read)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Read)
    //     else if (EL2Enabled() && (ELIsInHost(EL0) || (AArch64.HCR_EL2.DC):(AArch64.HCR_EL2.VM) == '00'))
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Read)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_12, EL1, ATAccess_Read)
}


/**
 * A64.AT S12E1W - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '0111', 'CRm': '1000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S12E1W(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (   (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & UINT64_C(0x1001) /*DC,VM*/))
        return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 1, kIemCImplA64ATAccess_Write);
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_12, 1, kIemCImplA64ATAccess_Write);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0) || (AArch64.HCR_EL2.DC):(AArch64.HCR_EL2.VM) == '00')
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Write)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_12, EL1, ATAccess_Write)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Write)
    //     else if (EL2Enabled() && (ELIsInHost(EL0) || (AArch64.HCR_EL2.DC):(AArch64.HCR_EL2.VM) == '00'))
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL1, ATAccess_Write)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_12, EL1, ATAccess_Write)
}


/**
 * A64.AT S12E0R - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '0111', 'CRm': '1000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S12E0R(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (   (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & UINT64_C(0x1001) /*DC,VM*/))
        return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 0, kIemCImplA64ATAccess_Read);
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_12, 0, kIemCImplA64ATAccess_Read);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0) || (AArch64.HCR_EL2.DC):(AArch64.HCR_EL2.VM) == '00')
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Read)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_12, EL0, ATAccess_Read)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Read)
    //     else if (EL2Enabled() && (ELIsInHost(EL0) || (AArch64.HCR_EL2.DC):(AArch64.HCR_EL2.VM) == '00'))
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Read)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_12, EL0, ATAccess_Read)
}


/**
 * A64.AT S12E0W - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '0111', 'CRm': '1000', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S12E0W(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (   (   pGstFeats->fVhe
            && pGstFeats->fEl2
            && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
            && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        || !(pVCpu->cpum.GstCtx.HcrEl2.u64 & UINT64_C(0x1001) /*DC,VM*/))
        return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 0, kIemCImplA64ATAccess_Write);
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_12, 0, kIemCImplA64ATAccess_Write);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0) || (AArch64.HCR_EL2.DC):(AArch64.HCR_EL2.VM) == '00')
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Write)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_12, EL0, ATAccess_Write)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Write)
    //     else if (EL2Enabled() && (ELIsInHost(EL0) || (AArch64.HCR_EL2.DC):(AArch64.HCR_EL2.VM) == '00'))
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL0, ATAccess_Write)
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_12, EL0, ATAccess_Write)
}


/**
 * A64.AT S1E2A - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '0111', 'CRm': '1001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E2A(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fATs1a)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64SysAt(pVCpu, uValue, kIemCImplA64TranslationStage_1, 2, kIemCImplA64ATAccess_Any);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_ATS1A))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL2, ATAccess_Any)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else
    //         AArch64_AT(X<t,0x40>, TranslationStage_1, EL2, ATAccess_Any)
}


/**
 * A64.TLBI IPAS2E1IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2E1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Ish,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_ISH,
    //                        TLBILevel_Any,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_ISH,
    //                        TLBILevel_Any,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2E1IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2E1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI IPAS2LE1IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2LE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Ish,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_ISH,
    //                        TLBILevel_Last,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_ISH,
    //                        TLBILevel_Last,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2LE1IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2LE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ALLE2OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE2OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiAll(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAE2OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE2OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Osh,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ALLE1OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VALE2OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE2OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Osh,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VMALLS12E1OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLS12E1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllS12(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID_NONE, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI RVAE2IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE2IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VMALLWS2E1IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLWS2E1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbiW)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllWs2(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIW))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI RVALE2IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE2IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI ALLE2IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE2IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiAll(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAE2IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE2IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Ish,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ALLE1IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0011', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VALE2IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE2IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Ish,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VMALLS12E1IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0011', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLS12E1IS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllS12(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID_NONE, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI IPAS2E1OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2E1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Osh,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_OSH,
    //                        TLBILevel_Any,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_OSH,
    //                        TLBILevel_Any,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI IPAS2E1 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2E1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Nsh,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_NSH,
    //                        TLBILevel_Any,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_NSH,
    //                        TLBILevel_Any,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2E1 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2E1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2E1OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2E1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI IPAS2LE1OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2LE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Osh,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_OSH,
    //                        TLBILevel_Last,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_OSH,
    //                        TLBILevel_Last,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI IPAS2LE1 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2LE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Nsh,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_NSH,
    //                        TLBILevel_Last,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_NSH,
    //                        TLBILevel_Last,
    //                        TLBI_AllAttr,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2LE1 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2LE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2LE1OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2LE1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI RVAE2OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE2OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VMALLWS2E1OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0101', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLWS2E1OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbiW)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllWs2(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIW))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI RVALE2OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE2OS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAE2 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VMALLWS2E1 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0110', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLWS2E1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbiW)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllWs2(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIW))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI RVALE2 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI ALLE2 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiAll(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     uValue);
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAE2 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Nsh,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ALLE1 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0111', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VALE2 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE2(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Nsh,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_AllAttr,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VMALLS12E1 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0111', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLS12E1(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllS12(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID_NONE, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI IPAS2E1ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2E1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Ish,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_ISH,
    //                        TLBILevel_Any,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_ISH,
    //                        TLBILevel_Any,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2E1ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2E1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI IPAS2LE1ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2LE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Ish,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_ISH,
    //                        TLBILevel_Last,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_ISH,
    //                        TLBILevel_Last,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2LE1ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2LE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ALLE2OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE2OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiAll(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAE2OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE2OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Osh,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ALLE1OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VALE2OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE2OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Osh,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VMALLS12E1OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0001', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLS12E1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllS12(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID_NONE, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI RVAE2ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE2ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VMALLWS2E1ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0010', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLWS2E1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbiW)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllWs2(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIW))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI RVALE2ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE2ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI ALLE2ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE2ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiAll(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAE2ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE2ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Ish,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ALLE1ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0011', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VALE2ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE2ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Ish,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VMALLS12E1ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0011', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLS12E1ISNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllS12(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID_NONE, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI IPAS2E1OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2E1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Osh,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_OSH,
    //                        TLBILevel_Any,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_OSH,
    //                        TLBILevel_Any,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI IPAS2E1NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2E1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Nsh,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_NSH,
    //                        TLBILevel_Any,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_NSH,
    //                        TLBILevel_Any,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2E1NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2E1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2E1OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2E1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI IPAS2LE1OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2LE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Osh,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_OSH,
    //                        TLBILevel_Last,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_OSH,
    //                        TLBILevel_Last,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI IPAS2LE1NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_IPAS2LE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiIpAs2(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Nsh,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_NSH,
    //                        TLBILevel_Last,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_IPAS2(SecurityStateAtEL(EL1),
    //                        Regime_EL10,
    //                        VMID<>,
    //                        Broadcast_NSH,
    //                        TLBILevel_Last,
    //                        TLBI_ExcludeXS,
    //                        X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2LE1NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2LE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI RIPAS2LE1OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RIPAS2LE1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiRIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_RIPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI RVAE2OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE2OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VMALLWS2E1OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0101', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLWS2E1OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbiW)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllWs2(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIW))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI RVALE2OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE2OSNXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange || !pGstFeats->fTlbios)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI RVAE2NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE2NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI VMALLWS2E1NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0110', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLWS2E1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbiW)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllWs2(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIW))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_VMALLWS2(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI RVALE2NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE2NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fTlbirange)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiRva(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiRva(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_RVA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          X<t,0x40>)
}


/**
 * A64.TLBI ALLE2NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE2NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiAll(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     uValue);
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL20, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_ALL(SecurityStateAtEL(EL2), Regime_EL2, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAE2NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE2NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Nsh,
                                kIemCImplA64TlbiLevel_Any,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI ALLE1NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0111', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiAll(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VALE2NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE2NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbiVa(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                    kIemCImplA64Regime_El20,
                                    0 /*VMID_NONE*/,
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    uValue);
    return iemCImplHlpA64TlbiVa(pVCpu,
                                iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                kIemCImplA64Regime_El2,
                                0 /*VMID_NONE*/,
                                kIemCImplA64Broadcast_Nsh,
                                kIemCImplA64TlbiLevel_Last,
                                kIemCImplA64TlbiMemAttr_ExcludeXs,
                                uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL20,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBI_VA(SecurityStateAtEL(EL2),
    //                         Regime_EL2,
    //                         VMID_NONE,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         X<t,0x40>)
}


/**
 * A64.TLBI VMALLS12E1NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0111', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VMALLS12E1NXS(PVMCPU pVCpu, uint64_t uValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbiVmAllS12(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      uValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x18)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID_NONE, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID<>, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.APAS  - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '0111', 'CRm': '0000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_APAS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME_GPC3))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     AArch64_APAS(X<t,0x40>)
}


/**
 * A64.DC CIPAPA - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '0111', 'CRm': '1110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIPAPA(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoPA)
}


/**
 * A64.DC CIGDPAPA - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '0111', 'CRm': '1110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_DC_CIGDPAPA(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_RME) && IsFeatureImplemented(FEAT_MTE2)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     AArch64_DC(X<t,0x40>, CacheType_Data_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoPA)
}


/**
 * A64.AT S1E3R - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '0111', 'CRm': '1000', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E3R(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL3, ATAccess_Read)
}


/**
 * A64.AT S1E3W - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '0111', 'CRm': '1000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E3W(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL3, ATAccess_Write)
}


/**
 * A64.AT S1E3A - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '0111', 'CRm': '1001', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_AT_S1E3A(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_ATS1A))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     AArch64_AT(X<t,0x40>, TranslationStage_1, EL3, ATAccess_Any)
}


/**
 * A64.TLBI ALLE3OS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE3OS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL3), Regime_EL3, Broadcast_OSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAE3OS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE3OS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_OSH,
    //                     TLBILevel_Any,
    //                     TLBI_AllAttr,
    //                     X<t,0x40>)
}


/**
 * A64.TLBI PAALLOS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0001', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_PAALLOS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     AArch64_TLBI_PAALL(Broadcast_OSH)
}


/**
 * A64.TLBI VALE3OS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE3OS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_OSH,
    //                     TLBILevel_Last,
    //                     TLBI_AllAttr,
    //                     X<t,0x40>)
}


/**
 * A64.TLBI RVAE3IS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE3IS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_ISH,
    //                      TLBILevel_Any,
    //                      TLBI_AllAttr,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI RVALE3IS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE3IS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_ISH,
    //                      TLBILevel_Last,
    //                      TLBI_AllAttr,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI ALLE3IS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE3IS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL3), Regime_EL3, Broadcast_ISH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAE3IS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE3IS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_ISH,
    //                     TLBILevel_Any,
    //                     TLBI_AllAttr,
    //                     X<t,0x40>)
}


/**
 * A64.TLBI VALE3IS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE3IS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_ISH,
    //                     TLBILevel_Last,
    //                     TLBI_AllAttr,
    //                     X<t,0x40>)
}


/**
 * A64.TLBI RPAOS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RPAOS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     AArch64_TLBI_RPA(TLBILevel_Any, X<t,0x40>, Broadcast_OSH)
}


/**
 * A64.TLBI RPALOS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RPALOS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     AArch64_TLBI_RPA(TLBILevel_Last, X<t,0x40>, Broadcast_OSH)
}


/**
 * A64.TLBI RVAE3OS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE3OS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_OSH,
    //                      TLBILevel_Any,
    //                      TLBI_AllAttr,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI RVALE3OS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE3OS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_OSH,
    //                      TLBILevel_Last,
    //                      TLBI_AllAttr,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI RVAE3 - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_NSH,
    //                      TLBILevel_Any,
    //                      TLBI_AllAttr,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI RVALE3 - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_NSH,
    //                      TLBILevel_Last,
    //                      TLBI_AllAttr,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI ALLE3 - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL3), Regime_EL3, Broadcast_NSH, TLBI_AllAttr, X<t,0x40>)
}


/**
 * A64.TLBI VAE3 - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_NSH,
    //                     TLBILevel_Any,
    //                     TLBI_AllAttr,
    //                     X<t,0x40>)
}


/**
 * A64.TLBI PAALL - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0111', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_PAALL(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_RME))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     AArch64_TLBI_PAALL(Broadcast_NSH)
}


/**
 * A64.TLBI VALE3 - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE3(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_NSH,
    //                     TLBILevel_Last,
    //                     TLBI_AllAttr,
    //                     X<t,0x40>)
}


/**
 * A64.TLBI ALLE3OSNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0001', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE3OSNXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL3), Regime_EL3, Broadcast_OSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAE3OSNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE3OSNXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_OSH,
    //                     TLBILevel_Any,
    //                     TLBI_ExcludeXS,
    //                     X<t,0x40>)
}


/**
 * A64.TLBI VALE3OSNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE3OSNXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIOS))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_OSH,
    //                     TLBILevel_Last,
    //                     TLBI_ExcludeXS,
    //                     X<t,0x40>)
}


/**
 * A64.TLBI RVAE3ISNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE3ISNXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_ISH,
    //                      TLBILevel_Any,
    //                      TLBI_ExcludeXS,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI RVALE3ISNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE3ISNXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_ISH,
    //                      TLBILevel_Last,
    //                      TLBI_ExcludeXS,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI ALLE3ISNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0011', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE3ISNXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL3), Regime_EL3, Broadcast_ISH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAE3ISNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE3ISNXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_ISH,
    //                     TLBILevel_Any,
    //                     TLBI_ExcludeXS,
    //                     X<t,0x40>)
}


/**
 * A64.TLBI VALE3ISNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE3ISNXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_ISH,
    //                     TLBILevel_Last,
    //                     TLBI_ExcludeXS,
    //                     X<t,0x40>)
}


/**
 * A64.TLBI RVAE3OSNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE3OSNXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_OSH,
    //                      TLBILevel_Any,
    //                      TLBI_ExcludeXS,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI RVALE3OSNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE3OSNXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS)))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_OSH,
    //                      TLBILevel_Last,
    //                      TLBI_ExcludeXS,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI RVAE3NXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVAE3NXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_NSH,
    //                      TLBILevel_Any,
    //                      TLBI_ExcludeXS,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI RVALE3NXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_RVALE3NXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_TLBIRANGE))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_RVA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_NSH,
    //                      TLBILevel_Last,
    //                      TLBI_ExcludeXS,
    //                      X<t,0x40>)
}


/**
 * A64.TLBI ALLE3NXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0111', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_ALLE3NXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_ALL(SecurityStateAtEL(EL3), Regime_EL3, Broadcast_NSH, TLBI_ExcludeXS, X<t,0x40>)
}


/**
 * A64.TLBI VAE3NXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VAE3NXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_NSH,
    //                     TLBILevel_Any,
    //                     TLBI_ExcludeXS,
    //                     X<t,0x40>)
}


/**
 * A64.TLBI VALE3NXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sys_TLBI_VALE3NXS(PVMCPU pVCpu, uint64_t uValue) RT_NOEXCEPT
{
    RT_NOREF(uValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBI_VA(SecurityStateAtEL(EL3),
    //                     Regime_EL3,
    //                     VMID_NONE,
    //                     Broadcast_NSH,
    //                     TLBILevel_Last,
    //                     TLBI_ExcludeXS,
    //                     X<t,0x40>)
}

/**
 * Implements the A64.SYS instruction (generic).
 *
 * @returns Strict VBox status code.
 * @param   pVCpu       The cross context virtual CPU structure of the
 *                      calling thread.
 * @param   idSysReg    The system register to write (IPRT format).
 * @param   idxGprSrc   The source GPR register number (for exceptions).
 * @param   uValue      The value to write.
 */
DECLHIDDEN(VBOXSTRICTRC) iemCImplA64_sys_generic(PVMCPU pVCpu, uint32_t idSysReg, uint32_t idxGprSrc, uint64_t uValue)
{
    Log(("iemCImplA64_sys(%#x, %#RX64)\n", idSysReg, uValue));
    uint32_t const uInstrEssence = IEM_CIMPL_SYSREG_INSTR_ESSENCE_MAKE(idSysReg, idxGprSrc, 0, 0xf);
    switch (idSysReg)
    {
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_IC_IALLUIS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_IC_IALLUIS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,10,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CSW(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CSW(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,10,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CGSW(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CGSW(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,10,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CGDSW(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CGDSW(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,14,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CISW(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CISW(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,14,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIGSW(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CIGSW(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,14,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIGDSW(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CIGDSW(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,15,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIVAPS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CIVAPS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,15,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIGDVAPS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CIGDVAPS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,5,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_IC_IALLU(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_IC_IALLU(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_IVAC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_IVAC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,6,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_ISW(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_ISW(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,6,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_IGVAC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_IGVAC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,6,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_IGSW(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_IGSW(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_IGDVAC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_IGDVAC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,6,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_IGDSW(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_IGDSW(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,7,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_GCSPUSHX(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_GCSPUSHX(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_GCSPOPCX(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_GCSPOPCX(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,7,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_GCSPOPX(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_GCSPOPX(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,8,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E1R(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S1E1R(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,8,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E1W(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S1E1W(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,8,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E0R(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S1E0R(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,8,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E0W(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S1E0W(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,9,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E1RP(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S1E1RP(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,9,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E1WP(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S1E1WP(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,7,9,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E1A(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S1E1A(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ASIDE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ASIDE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,1,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAAE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAAE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,1,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAALE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAALE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAAE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAAE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,2,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAALE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAALE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ASIDE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ASIDE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,3,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAAE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAAE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,3,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAALE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAALE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,5,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAAE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAAE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,5,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAALE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAALE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,6,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAAE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAAE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,6,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAALE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAALE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,7,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,7,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ASIDE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ASIDE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAAE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAAE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,7,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAALE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAALE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,1,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ASIDE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ASIDE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,1,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAAE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAAE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,1,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAALE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAALE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAAE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAAE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,2,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAALE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAALE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,3,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ASIDE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ASIDE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,3,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAAE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAAE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,3,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAALE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAALE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,5,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAAE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAAE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,5,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAALE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAALE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,6,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAAE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAAE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,6,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAALE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAALE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,7,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,7,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ASIDE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ASIDE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAAE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAAE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,7,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAALE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAALE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,1,7,2,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_BRB_IALL(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_BRB_IALL(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,1,7,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_BRB_INJ(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_BRB_INJ(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,10,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CVAC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CVAC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,10,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CGVAC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CGVAC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,10,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CGDVAC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CGDVAC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,11,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CVAOC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CVAOC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,11,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CVAU(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CVAU(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,11,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CGDVAOC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CGDVAOC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,12,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CVAP(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CVAP(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,12,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CGVAP(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CGVAP(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,12,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CGDVAP(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CGDVAP(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,13,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CVADP(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CVADP(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,13,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CGVADP(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CGVADP(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,13,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CGDVADP(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CGDVADP(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,14,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIVAC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CIVAC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,14,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIGVAC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CIGVAC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,14,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIGDVAC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CIGDVAC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,15,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIVAOC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CIVAOC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,15,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIGDVAOC(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_CIGDVAOC(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,2,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TRCIT(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TRCIT(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,3,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_CFP_RCTX(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_CFP_RCTX(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DVP_RCTX(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DVP_RCTX(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,3,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_COSP_RCTX(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_COSP_RCTX(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,3,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_CPP_RCTX(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_CPP_RCTX(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_ZVA(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_ZVA(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_GVA(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_GVA(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_GZVA(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_DC_GZVA(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_IC_IVAU(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_IC_IVAU(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,7,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_GCSPUSHM(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_GCSPUSHM(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,7,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_GCSSS1(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_GCSSS1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,7,14,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIPAE(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_DC_CIPAE(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,7,14,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIGDPAE(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_DC_CIGDPAE(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,7,8,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E2R(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S1E2R(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,7,8,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E2W(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S1E2W(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,7,8,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S12E1R(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S12E1R(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,7,8,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S12E1W(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S12E1W(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,7,8,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S12E0R(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S12E0R(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,7,8,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S12E0W(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S12E0W(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,7,9,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E2A(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_AT_S1E2A(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2E1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2E1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2E1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2E1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2LE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2LE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2LE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2LE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE2OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE2OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE2OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE2OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE2OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE2OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,1,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLS12E1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLS12E1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE2IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE2IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLWS2E1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLWS2E1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE2IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE2IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE2IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE2IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE2IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE2IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,3,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE2IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE2IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,3,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLS12E1IS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLS12E1IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2E1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2E1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2E1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2E1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2E1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2E1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2E1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2E1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2LE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2LE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2LE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2LE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2LE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2LE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2LE1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2LE1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE2OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE2OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,5,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLWS2E1OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLWS2E1OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE2OS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE2OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,6,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLWS2E1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLWS2E1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,7,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,7,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE2(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE2(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,7,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLS12E1(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLS12E1(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2E1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2E1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2E1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2E1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2LE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2LE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2LE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2LE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE2OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE2OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE2OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE2OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE2OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE2OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,1,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLS12E1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLS12E1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE2ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE2ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,2,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLWS2E1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLWS2E1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE2ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE2ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE2ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE2ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE2ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE2ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,3,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE2ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE2ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,3,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLS12E1ISNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLS12E1ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2E1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2E1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2E1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2E1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2E1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2E1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2E1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2E1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2LE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2LE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_IPAS2LE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_IPAS2LE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2LE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2LE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RIPAS2LE1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RIPAS2LE1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE2OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE2OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,5,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLWS2E1OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLWS2E1OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE2OSNXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE2OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE2NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE2NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,6,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLWS2E1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLWS2E1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE2NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE2NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,7,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE2NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE2NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE2NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VAE2NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,7,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE2NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VALE2NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,7,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VMALLS12E1NXS(pVCpu, uValue, uInstrEssence);
            LogFlow(("iemCImplA64_sys_TLBI_VMALLS12E1NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,7,0,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_APAS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_APAS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,7,14,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIPAPA(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_DC_CIPAPA(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,7,14,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_DC_CIGDPAPA(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_DC_CIGDPAPA(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,7,8,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E3R(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_AT_S1E3R(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,7,8,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E3W(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_AT_S1E3W(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,7,9,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_AT_S1E3A(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_AT_S1E3A(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE3OS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE3OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE3OS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VAE3OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,1,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_PAALLOS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_PAALLOS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE3OS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VALE3OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE3IS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE3IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE3IS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE3IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE3IS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE3IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE3IS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VAE3IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE3IS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VALE3IS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RPAOS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RPAOS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,4,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RPALOS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RPALOS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE3OS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE3OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE3OS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE3OS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE3(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE3(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,7,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE3(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE3(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VAE3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,7,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_PAALL(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_PAALL(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE3(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VALE3(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,1,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE3OSNXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE3OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE3OSNXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VAE3OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE3OSNXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VALE3OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE3ISNXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE3ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE3ISNXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE3ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,3,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE3ISNXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE3ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE3ISNXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VAE3ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE3ISNXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VALE3ISNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE3OSNXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE3OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE3OSNXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE3OSNXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVAE3NXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVAE3NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_RVALE3NXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_RVALE3NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,7,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_ALLE3NXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_ALLE3NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VAE3NXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VAE3NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sys_TLBI_VALE3NXS(pVCpu, uValue);
            LogFlow(("iemCImplA64_sys_TLBI_VALE3NXS(%#RX64) -> %Rrc\n", uValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
    }
    /* Fall back on handcoded handler. */
    return iemCImplA64_sys_fallback(pVCpu, idSysReg, idxGprSrc, uValue);
}

/**
 * Implements the A64.SYS instruction.
 *
 * @param   idSysReg    The system register to write (IPRT format).
 * @param   idxGprSrc   The source GPR register number (for exceptions).
 */
IEM_CIMPL_DEF_2(iemCImplA64_sys, uint32_t, idSysReg, uint32_t, idxGprSrc)
{
    uint64_t const uValue = idxGprSrc < ARMV8_A64_REG_XZR ? pVCpu->cpum.GstCtx.aGRegs[idxGprSrc].x : 0;
    return iemCImplA64_sys_generic(pVCpu, idSysReg, idxGprSrc, uValue);
}



/*
 * A64.SYSL
 *
 *    2 registers
 *    2 complete - 0 with unresolved registers
 *    0 incomplete
 */


/**
 * A64.GCSPOPM  - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysl_GCSPOPM(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (iemCImplHlpIsGcsEnabledAtCurrentEl(pVCpu))
        return iemCImplHlpA64GcsPopM(pVCpu, puDst);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (GCSEnabled(PSTATE.EL))
    //     X<t,0x40> = GCSPOPM();
}


/**
 * A64.GCSSS2  - OrderedDict({'op0': '01', 'op1': '011', 'CRn': '0111', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysl_GCSSS2(PVMCPU pVCpu, uint64_t * puDst) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fGcs)
        return iemRaiseUndefined(pVCpu);
    if (iemCImplHlpIsGcsEnabledAtCurrentEl(pVCpu))
        return iemCImplHlpA64GcsSs2(pVCpu, puDst);
    return iemRegPcA64IncAndFinishingClearingFlags(pVCpu, VINF_SUCCESS);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_GCS))
    //     Undefined()
    // else if (GCSEnabled(PSTATE.EL))
    //     X<t,0x40> = GCSSS2();
}

/**
 * Implements the A64.SYSL instruction (generic).
 *
 * @returns Strict VBox status code.
 * @param   pVCpu       The cross context virtual CPU structure of the
 *                      calling thread.
 * @param   idSysReg    The system register to read (IPRT format).
 * @param   idxGprDst   The destination GPR register number (for exceptions).
 * @param   puDst       Where to return the value.
 */
DECLHIDDEN(VBOXSTRICTRC) iemCImplA64_sysl_generic(PVMCPU pVCpu, uint32_t idSysReg, uint32_t idxGprDst, uint64_t * puDst)
{
    Log(("iemCImplA64_sysl(%#x)\n", idSysReg));
    switch (idSysReg)
    {
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysl_GCSPOPM(pVCpu, puDst);
            LogFlow(("iemCImplA64_sysl_GCSPOPM -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,3,7,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysl_GCSSS2(pVCpu, puDst);
            LogFlow(("iemCImplA64_sysl_GCSSS2 -> %Rrc & *puDst=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), *puDst));
            return rcStrict;
        }
    }
    /* Fall back on handcoded handler. */
    return iemCImplA64_sysl_fallback(pVCpu, idSysReg, idxGprDst, puDst);
}

/**
 * Implements the A64.SYSL instruction.
 *
 * @param   idSysReg    The system register to read (IPRT format).
 * @param   idxGprDst   The destination GPR register number (for exceptions).
 */
IEM_CIMPL_DEF_2(iemCImplA64_sysl, uint32_t, idSysReg, uint32_t, idxGprDst)
{
    uint64_t         uZeroDummy;
    uint64_t * const puDst = idxGprDst < ARMV8_A64_REG_XZR
                           ? &pVCpu->cpum.GstCtx.aGRegs[idxGprDst].x : &uZeroDummy;
    return iemCImplA64_sysl_generic(pVCpu, idSysReg, idxGprDst, puDst);
}



/*
 * A64.SYSP
 *
 *  120 registers
 *  120 complete - 0 with unresolved registers
 *    0 incomplete
 */


/**
 * A64.TLBIP VAE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAAE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAAE1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAALE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0001', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAALE1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAAE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAAE1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Ish,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_ISH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_ISH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAALE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0010', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAALE1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Ish,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_ISH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_ISH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAAE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAAE1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAALE1IS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0011', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAALE1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAAE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAAE1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Osh,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_OSH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_OSH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAALE1OS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0101', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAALE1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Osh,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_OSH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_OSH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipRva(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Any,
                                          kIemCImplA64TlbiMemAttr_AllAttr,
                                          puValue);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Any,
    //                               TLBI_ExcludeXS,
    //                               (X<t2,0x40>):(X<t,0x40>))
    //         else
    //             AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Any,
    //                               TLBI_AllAttr,
    //                               (X<t2,0x40>):(X<t,0x40>))
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAAE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0110', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAAE1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipRvaa(pVCpu,
                                           iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                           kIemCImplA64Regime_El10,
                                           iemCImplHlpGetCurrentVmId(pVCpu),
                                           kIemCImplA64Broadcast_ForcedIsh,
                                           kIemCImplA64TlbiLevel_Any,
                                           kIemCImplA64TlbiMemAttr_AllAttr,
                                           puValue);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Nsh,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                                Regime_EL10,
    //                                VMID<>,
    //                                Broadcast_ForcedISH,
    //                                TLBILevel_Any,
    //                                TLBI_ExcludeXS,
    //                                (X<t2,0x40>):(X<t,0x40>))
    //         else
    //             AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                                Regime_EL10,
    //                                VMID<>,
    //                                Broadcast_ForcedISH,
    //                                TLBILevel_Any,
    //                                TLBI_AllAttr,
    //                                (X<t2,0x40>):(X<t,0x40>))
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_NSH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_NSH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Any,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipRva(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Last,
                                          kIemCImplA64TlbiMemAttr_AllAttr,
                                          puValue);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Last,
    //                               TLBI_ExcludeXS,
    //                               (X<t2,0x40>):(X<t,0x40>))
    //         else
    //             AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Last,
    //                               TLBI_AllAttr,
    //                               (X<t2,0x40>):(X<t,0x40>))
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAALE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAALE1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipRvaa(pVCpu,
                                           iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                           kIemCImplA64Regime_El10,
                                           iemCImplHlpGetCurrentVmId(pVCpu),
                                           kIemCImplA64Broadcast_ForcedIsh,
                                           kIemCImplA64TlbiLevel_Last,
                                           kIemCImplA64TlbiMemAttr_AllAttr,
                                           puValue);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_AllAttr,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Nsh,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_AllAttr,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                                Regime_EL10,
    //                                VMID<>,
    //                                Broadcast_ForcedISH,
    //                                TLBILevel_Last,
    //                                TLBI_ExcludeXS,
    //                                (X<t2,0x40>):(X<t,0x40>))
    //         else
    //             AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                                Regime_EL10,
    //                                VMID<>,
    //                                Broadcast_ForcedISH,
    //                                TLBILevel_Last,
    //                                TLBI_AllAttr,
    //                                (X<t2,0x40>):(X<t,0x40>))
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_NSH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_NSH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Last,
    //                            TLBI_AllAttr,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipVa(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Any,
                                         kIemCImplA64TlbiMemAttr_AllAttr,
                                         puValue);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Any,
    //                              TLBI_ExcludeXS,
    //                              (X<t2,0x40>):(X<t,0x40>))
    //         else
    //             AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Any,
    //                              TLBI_AllAttr,
    //                              (X<t2,0x40>):(X<t,0x40>))
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAAE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAAE1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipVaa(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Any,
                                          kIemCImplA64TlbiMemAttr_AllAttr,
                                          puValue);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Any,
    //                               TLBI_ExcludeXS,
    //                               (X<t2,0x40>):(X<t,0x40>))
    //         else
    //             AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Any,
    //                               TLBI_AllAttr,
    //                               (X<t2,0x40>):(X<t,0x40>))
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipVa(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Last,
                                         kIemCImplA64TlbiMemAttr_AllAttr,
                                         puValue);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Last,
    //                              TLBI_ExcludeXS,
    //                              (X<t2,0x40>):(X<t,0x40>))
    //         else
    //             AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                              Regime_EL10,
    //                              VMID<>,
    //                              Broadcast_ForcedISH,
    //                              TLBILevel_Last,
    //                              TLBI_AllAttr,
    //                              (X<t2,0x40>):(X<t,0x40>))
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAALE1 - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1000', 'CRm': '0111', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAALE1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipVaa(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Last,
                                          kIemCImplA64TlbiMemAttr_AllAttr,
                                          puValue);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         if (   IsFeatureImplemented(FEAT_XS)
    //             && IsFeatureImplemented(FEAT_HCX)
    //             && IsHCRXEL2Enabled()
    //             && AArch64.HCRX_EL2.FnXS == '1')
    //             AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Last,
    //                               TLBI_ExcludeXS,
    //                               (X<t2,0x40>):(X<t,0x40>))
    //         else
    //             AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                               Regime_EL10,
    //                               VMID<>,
    //                               Broadcast_ForcedISH,
    //                               TLBILevel_Last,
    //                               TLBI_AllAttr,
    //                               (X<t2,0x40>):(X<t,0x40>))
    //     else if (   IsFeatureImplemented(FEAT_XS)
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && IsHCRXEL2Enabled()
    //              && AArch64.HCRX_EL2.FnXS == '1')
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAAE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0001', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAAE1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAALE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0001', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAALE1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAAE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0010', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAAE1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Ish,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_ISH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_ISH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAALE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0010', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAALE1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Ish,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Ish,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_ISH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_ISH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ISH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAAE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0011', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAAE1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAALE1ISNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0011', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAALE1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(54)/*TTLBIS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBIS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1IS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAAE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0101', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAAE1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Osh,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_OSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_OSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAALE1OSNXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0101', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAALE1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(55)/*TTLBOS*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Osh,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Osh,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.TTLBOS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1OS == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_OSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_OSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_OSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipRva(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Any,
                                          kIemCImplA64TlbiMemAttr_ExcludeXs,
                                          puValue);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ForcedISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAAE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0110', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAAE1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipRvaa(pVCpu,
                                           iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                           kIemCImplA64Regime_El10,
                                           iemCImplHlpGetCurrentVmId(pVCpu),
                                           kIemCImplA64Broadcast_ForcedIsh,
                                           kIemCImplA64TlbiLevel_Any,
                                           kIemCImplA64TlbiMemAttr_ExcludeXs,
                                           puValue);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiLevel_Any,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Nsh,
                                   kIemCImplA64TlbiLevel_Any,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ForcedISH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_NSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_NSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Any,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipRva(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Last,
                                          kIemCImplA64TlbiMemAttr_ExcludeXs,
                                          puValue);
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ForcedISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAALE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0110', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAALE1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipRvaa(pVCpu,
                                           iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                           kIemCImplA64Regime_El10,
                                           iemCImplHlpGetCurrentVmId(pVCpu),
                                           kIemCImplA64Broadcast_ForcedIsh,
                                           kIemCImplA64TlbiLevel_Last,
                                           kIemCImplA64TlbiMemAttr_ExcludeXs,
                                           puValue);
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                       kIemCImplA64Regime_El10,
                                       iemCImplHlpGetCurrentVmId(pVCpu),
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipRvaa(pVCpu,
                                       iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                       kIemCImplA64Regime_El20,
                                       0 /*VMID_NONE*/,
                                       kIemCImplA64Broadcast_Nsh,
                                       kIemCImplA64TlbiLevel_Last,
                                       kIemCImplA64TlbiMemAttr_ExcludeXs,
                                       puValue);
    return iemCImplHlpA64TlbipRvaa(pVCpu,
                                   iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                   kIemCImplA64Regime_El10,
                                   iemCImplHlpGetCurrentVmId(pVCpu),
                                   kIemCImplA64Broadcast_Nsh,
                                   kIemCImplA64TlbiLevel_Last,
                                   kIemCImplA64TlbiMemAttr_ExcludeXs,
                                   puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIRVAALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_ForcedISH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_NSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL2),
    //                            Regime_EL20,
    //                            VMID_NONE,
    //                            Broadcast_NSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1),
    //                            Regime_EL10,
    //                            VMID<>,
    //                            Broadcast_NSH,
    //                            TLBILevel_Last,
    //                            TLBI_ExcludeXS,
    //                            (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipVa(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Any,
                                         kIemCImplA64TlbiMemAttr_ExcludeXs,
                                         puValue);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ForcedISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAAE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0111', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAAE1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipVaa(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Any,
                                          kIemCImplA64TlbiMemAttr_ExcludeXs,
                                          puValue);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAAE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ForcedISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipVa(pVCpu,
                                         iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                         kIemCImplA64Regime_El10,
                                         iemCImplHlpGetCurrentVmId(pVCpu),
                                         kIemCImplA64Broadcast_ForcedIsh,
                                         kIemCImplA64TlbiLevel_Last,
                                         kIemCImplA64TlbiMemAttr_ExcludeXs,
                                         puValue);
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                 kIemCImplA64Regime_El10,
                                 iemCImplHlpGetCurrentVmId(pVCpu),
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ForcedISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAALE1NXS - OrderedDict({'op0': '01', 'op1': '000', 'CRn': '1001', 'CRm': '0111', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAALE1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(25)/*TTLB*/))
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        if (pGstFeats->fEl2 && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(9)/*FB*/))
            return iemCImplHlpA64TlbipVaa(pVCpu,
                                          iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                          kIemCImplA64Regime_El10,
                                          iemCImplHlpGetCurrentVmId(pVCpu),
                                          kIemCImplA64Broadcast_ForcedIsh,
                                          kIemCImplA64TlbiLevel_Last,
                                          kIemCImplA64TlbiMemAttr_ExcludeXs,
                                          puValue);
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                      kIemCImplA64Regime_El10,
                                      iemCImplHlpGetCurrentVmId(pVCpu),
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    }
    if (   pGstFeats->fVhe
        && pGstFeats->fEl2
        && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/))
        && (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_32(27)/*TGE*/))
        return iemCImplHlpA64TlbipVaa(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipVaa(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                  kIemCImplA64Regime_El10,
                                  iemCImplHlpGetCurrentVmId(pVCpu),
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EL2Enabled() && AArch64.HCR_EL2.TTLB == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (   EL2Enabled()
    //              && IsFeatureImplemented(FEAT_FGT)
    //              && (!HaveEL(EL3) || AArch64.SCR_EL3.FGTEn == '1')
    //              && IsFeatureImplemented(FEAT_HCX)
    //              && (!IsHCRXEL2Enabled() || AArch64.HCRX_EL2.FGTnXS == '0')
    //              && AArch64.HFGITR_EL2.TLBIVAALE1 == '1')
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else if (EL2Enabled() && AArch64.HCR_EL2.FB == '1')
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_ForcedISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL0))
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (ELIsInHost(EL0))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     else
    //         AArch64_TLBIP_VAA(SecurityStateAtEL(EL1),
    //                           Regime_EL10,
    //                           VMID<>,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2E1IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2E1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2E1IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2E1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2LE1IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2LE1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2LE1IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2LE1IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE2OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE2OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE2OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE2OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE2IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE2IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE2IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE2IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE2IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE2IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE2IS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE2IS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2E1OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2E1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2E1 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2E1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2E1 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2E1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2E1OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2E1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2LE1OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2LE1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2LE1 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2LE1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_AllAttr,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_AllAttr,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2LE1 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2LE1(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2LE1OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2LE1OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE2OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE2OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE2OS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE2OS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE2 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE2(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE2 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE2(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_AllAttr,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_AllAttr,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_AllAttr,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE2 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE2(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE2 - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1000', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE2(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_AllAttr,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_AllAttr,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_AllAttr,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2E1ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0000', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2E1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2E1ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0000', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2E1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2LE1ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0000', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2LE1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Ish,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_ISH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2LE1ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0000', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2LE1ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE2OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE2OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE2OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE2OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Osh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE2ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE2ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE2ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE2ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Ish,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Ish,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_ISH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE2ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE2ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE2ISNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE2ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Ish,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Ish,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_ISH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2E1OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '000'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2E1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2E1NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2E1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Any,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Any,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2E1NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '010'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2E1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2E1OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '011'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2E1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2LE1OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '100'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2LE1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Osh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_OSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP IPAS2LE1NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_IPAS2LE1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipIpAs2(pVCpu,
                                    iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                    kIemCImplA64Regime_El10,
                                    iemCImplHlpGetCurrentVmId(pVCpu),
                                    kIemCImplA64Broadcast_Nsh,
                                    kIemCImplA64TlbiLevel_Last,
                                    kIemCImplA64TlbiMemAttr_ExcludeXs,
                                    puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_IPAS2(SecurityStateAtEL(EL1),
    //                         Regime_EL10,
    //                         VMID<>,
    //                         Broadcast_NSH,
    //                         TLBILevel_Last,
    //                         TLBI_ExcludeXS,
    //                         (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2LE1NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '110'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2LE1NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RIPAS2LE1OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0100', 'op2': '111'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RIPAS2LE1OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    return iemCImplHlpA64TlbipRIpAs2(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 1),
                                     kIemCImplA64Regime_El10,
                                     iemCImplHlpGetCurrentVmId(pVCpu),
                                     kIemCImplA64Broadcast_Osh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         return;
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1))
    //         return;
    //     AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1),
    //                          Regime_EL10,
    //                          VMID<>,
    //                          Broadcast_OSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE2OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE2OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE2OSNXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE2OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Osh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Osh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_OSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE2NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE2NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Any,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Any,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Any,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE2NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE2NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipRva(pVCpu,
                                      iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                      kIemCImplA64Regime_El20,
                                      0 /*VMID_NONE*/,
                                      kIemCImplA64Broadcast_Nsh,
                                      kIemCImplA64TlbiLevel_Last,
                                      kIemCImplA64TlbiMemAttr_ExcludeXs,
                                      puValue);
    return iemCImplHlpA64TlbipRva(pVCpu,
                                  iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                  kIemCImplA64Regime_El2,
                                  0 /*VMID_NONE*/,
                                  kIemCImplA64Broadcast_Nsh,
                                  kIemCImplA64TlbiLevel_Last,
                                  kIemCImplA64TlbiMemAttr_ExcludeXs,
                                  puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL20,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_RVA(SecurityStateAtEL(EL2),
    //                           Regime_EL2,
    //                           VMID_NONE,
    //                           Broadcast_NSH,
    //                           TLBILevel_Last,
    //                           TLBI_ExcludeXS,
    //                           (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE2NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE2NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Any,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Any,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Any,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE2NXS - OrderedDict({'op0': '01', 'op1': '100', 'CRn': '1001', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE2NXS(PVMCPU pVCpu, PCRTUINT128U puValue, uint32_t uInstrEssence) RT_NOEXCEPT
{
    const CPUMFEATURESARMV8 * const pGstFeats = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
    if (!pGstFeats->fD128)
        return iemRaiseUndefined(pVCpu);
    if (!pGstFeats->fXs)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 0)
        return iemRaiseUndefined(pVCpu);
    if (IEM_F_MODE_ARM_GET_EL(ICORE(pVCpu).fExec) == 1)
    {
        if ((iemGetEffHcrEl2NVx(pVCpu, pGstFeats) & 1) == 1)
            return iemRaiseSystemAccessTrap128Bit(pVCpu, 2, uInstrEssence);
        return iemRaiseUndefined(pVCpu);
    }
    if (pGstFeats->fVhe && pGstFeats->fEl2 && (!pGstFeats->fE2H0 || (pVCpu->cpum.GstCtx.HcrEl2.u64 & RT_BIT_64(34)/*E2H*/)))
        return iemCImplHlpA64TlbipVa(pVCpu,
                                     iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                     kIemCImplA64Regime_El20,
                                     0 /*VMID_NONE*/,
                                     kIemCImplA64Broadcast_Nsh,
                                     kIemCImplA64TlbiLevel_Last,
                                     kIemCImplA64TlbiMemAttr_ExcludeXs,
                                     puValue);
    return iemCImplHlpA64TlbipVa(pVCpu,
                                 iemCImplHlpGetSecurityStateAtEl(pVCpu, 2),
                                 kIemCImplA64Regime_El2,
                                 0 /*VMID_NONE*/,
                                 kIemCImplA64Broadcast_Nsh,
                                 kIemCImplA64TlbiLevel_Last,
                                 kIemCImplA64TlbiMemAttr_ExcludeXs,
                                 puValue);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     if (EffectiveHCR_EL2_NVx() IN ('xx1'))
    //         AArch64_SystemAccessTrap(EL2, 0x14)
    //     else
    //         Undefined()
    // else if (PSTATE.EL == EL2)
    //     if (ELIsInHost(EL2))
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    // else if (PSTATE.EL == EL3)
    //     if (!EL2Enabled())
    //         Undefined()
    //     else if (ELIsInHost(EL2))
    //         if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //             return;
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL20,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
    //     else if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2))
    //         return;
    //     else
    //         AArch64_TLBIP_VA(SecurityStateAtEL(EL2),
    //                          Regime_EL2,
    //                          VMID_NONE,
    //                          Broadcast_NSH,
    //                          TLBILevel_Last,
    //                          TLBI_ExcludeXS,
    //                          (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE3OS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE3OS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_OSH,
    //                      TLBILevel_Any,
    //                      TLBI_AllAttr,
    //                      (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE3OS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE3OS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_OSH,
    //                      TLBILevel_Last,
    //                      TLBI_AllAttr,
    //                      (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE3IS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE3IS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_ISH,
    //                       TLBILevel_Any,
    //                       TLBI_AllAttr,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE3IS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE3IS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_ISH,
    //                       TLBILevel_Last,
    //                       TLBI_AllAttr,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE3IS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE3IS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_ISH,
    //                      TLBILevel_Any,
    //                      TLBI_AllAttr,
    //                      (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE3IS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE3IS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_ISH,
    //                      TLBILevel_Last,
    //                      TLBI_AllAttr,
    //                      (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE3OS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE3OS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_OSH,
    //                       TLBILevel_Any,
    //                       TLBI_AllAttr,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE3OS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE3OS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_OSH,
    //                       TLBILevel_Last,
    //                       TLBI_AllAttr,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE3 - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE3(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_NSH,
    //                       TLBILevel_Any,
    //                       TLBI_AllAttr,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE3 - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE3(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_NSH,
    //                       TLBILevel_Last,
    //                       TLBI_AllAttr,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE3 - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE3(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_NSH,
    //                      TLBILevel_Any,
    //                      TLBI_AllAttr,
    //                      (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE3 - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1000', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE3(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_NSH,
    //                      TLBILevel_Last,
    //                      TLBI_AllAttr,
    //                      (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE3OSNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0001', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE3OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_OSH,
    //                      TLBILevel_Any,
    //                      TLBI_ExcludeXS,
    //                      (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE3OSNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0001', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE3OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_OSH,
    //                      TLBILevel_Last,
    //                      TLBI_ExcludeXS,
    //                      (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE3ISNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0010', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE3ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_ISH,
    //                       TLBILevel_Any,
    //                       TLBI_ExcludeXS,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE3ISNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0010', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE3ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_ISH,
    //                       TLBILevel_Last,
    //                       TLBI_ExcludeXS,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE3ISNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0011', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE3ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_ISH,
    //                      TLBILevel_Any,
    //                      TLBI_ExcludeXS,
    //                      (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE3ISNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0011', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE3ISNXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_ISH,
    //                      TLBILevel_Last,
    //                      TLBI_ExcludeXS,
    //                      (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE3OSNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0101', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE3OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_OSH,
    //                       TLBILevel_Any,
    //                       TLBI_ExcludeXS,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE3OSNXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0101', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE3OSNXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_OSH,
    //                       TLBILevel_Last,
    //                       TLBI_ExcludeXS,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVAE3NXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0110', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVAE3NXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_NSH,
    //                       TLBILevel_Any,
    //                       TLBI_ExcludeXS,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP RVALE3NXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0110', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_RVALE3NXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_RVA(SecurityStateAtEL(EL3),
    //                       Regime_EL3,
    //                       VMID_NONE,
    //                       Broadcast_NSH,
    //                       TLBILevel_Last,
    //                       TLBI_ExcludeXS,
    //                       (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VAE3NXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0111', 'op2': '001'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VAE3NXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_NSH,
    //                      TLBILevel_Any,
    //                      TLBI_ExcludeXS,
    //                      (X<t2,0x40>):(X<t,0x40>))
}


/**
 * A64.TLBIP VALE3NXS - OrderedDict({'op0': '01', 'op1': '110', 'CRn': '1001', 'CRm': '0111', 'op2': '101'})
 * Transformation status: 0 - complete
 */
static VBOXSTRICTRC iemCImplA64_sysp_TLBIP_VALE3NXS(PVMCPU pVCpu, PCRTUINT128U puValue) RT_NOEXCEPT
{
    RT_NOREF(puValue);
    return iemRaiseUndefined(pVCpu);
    /* -------- Original code specification: -------- */
    // if (!IsFeatureImplemented(FEAT_D128))
    //     Undefined()
    // else if (!IsFeatureImplemented(FEAT_XS))
    //     Undefined()
    // else if (PSTATE.EL == EL0)
    //     Undefined()
    // else if (PSTATE.EL == EL1)
    //     Undefined()
    // else if (PSTATE.EL == EL2)
    //     Undefined()
    // else if (PSTATE.EL == EL3)
    //     if (IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3))
    //         return;
    //     AArch64_TLBIP_VA(SecurityStateAtEL(EL3),
    //                      Regime_EL3,
    //                      VMID_NONE,
    //                      Broadcast_NSH,
    //                      TLBILevel_Last,
    //                      TLBI_ExcludeXS,
    //                      (X<t2,0x40>):(X<t,0x40>))
}

/**
 * Implements the A64.SYSP instruction (generic).
 *
 * @returns Strict VBox status code.
 * @param   pVCpu       The cross context virtual CPU structure of the
 *                      calling thread.
 * @param   idSysReg    The system register to write (IPRT format).
 * @param   idxGprSrc   The source GPR register number (for exceptions).
 * @param   puValue     The value to write.
 */
DECLHIDDEN(VBOXSTRICTRC) iemCImplA64_sysp_generic(PVMCPU pVCpu, uint32_t idSysReg, uint32_t idxGprSrc, PCRTUINT128U puValue)
{
    Log(("iemCImplA64_sysp(%#x, %.16Rhxs)\n", idSysReg, puValue));
    uint32_t const uInstrEssence = IEM_CIMPL_SYSREG_INSTR_ESSENCE_MAKE(idSysReg, idxGprSrc, 0, 0xf);
    switch (idSysReg)
    {
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,1,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAAE1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAAE1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,1,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAALE1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAALE1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAAE1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAAE1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,2,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAALE1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAALE1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,3,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAAE1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAAE1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,3,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAALE1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAALE1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,5,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAAE1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAAE1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,5,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAALE1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAALE1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,6,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAAE1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAAE1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,6,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAALE1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAALE1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAAE1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAAE1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,8,7,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAALE1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAALE1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,1,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAAE1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAAE1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,1,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAALE1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAALE1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,2,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAAE1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAAE1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,2,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAALE1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAALE1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,3,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAAE1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAAE1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,3,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAALE1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAALE1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,5,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAAE1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAAE1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,5,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAALE1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAALE1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,6,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAAE1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAAE1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,6,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAALE1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAALE1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,7,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAAE1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAAE1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,0,9,7,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAALE1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAALE1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2E1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2E1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2E1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2E1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2LE1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2LE1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2LE1IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2LE1IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE2OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE2OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE2OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE2OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE2IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE2IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE2IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE2IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE2IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE2IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE2IS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE2IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2E1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2E1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2E1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2E1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2E1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2E1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2E1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2E1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2LE1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2LE1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2LE1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2LE1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2LE1(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2LE1(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,4,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2LE1OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2LE1OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE2OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE2OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE2OS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE2OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE2(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE2(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE2(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE2(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE2(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE2(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,8,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE2(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE2(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,0,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2E1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2E1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,0,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2E1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2E1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,0,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2LE1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2LE1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,0,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2LE1ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2LE1ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE2OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE2OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE2OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE2OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE2ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE2ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE2ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE2ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE2ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE2ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE2ISNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE2ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,0):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2E1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2E1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2E1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2E1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,2):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2E1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2E1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,3):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2E1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2E1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,4):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2LE1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2LE1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_IPAS2LE1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_IPAS2LE1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,6):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2LE1NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2LE1NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,4,7):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RIPAS2LE1OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RIPAS2LE1OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE2OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE2OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE2OSNXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE2OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE2NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE2NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE2NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE2NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE2NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE2NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,4,9,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE2NXS(pVCpu, puValue, uInstrEssence);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE2NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE3OS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE3OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE3OS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE3OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE3IS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE3IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE3IS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE3IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE3IS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE3IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE3IS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE3IS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE3OS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE3OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE3OS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE3OS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE3(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE3(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE3(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE3(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE3(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE3(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,8,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE3(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE3(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,1,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE3OSNXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE3OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,1,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE3OSNXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE3OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,2,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE3ISNXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE3ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,2,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE3ISNXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE3ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,3,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE3ISNXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE3ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,3,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE3ISNXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE3ISNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,5,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE3OSNXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE3OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,5,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE3OSNXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE3OSNXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,6,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVAE3NXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVAE3NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,6,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_RVALE3NXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_RVALE3NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,7,1):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VAE3NXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VAE3NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
        case ARMV8_AARCH64_SYSREG_ID_CREATE(1,6,9,7,5):
        {
            VBOXSTRICTRC const rcStrict = iemCImplA64_sysp_TLBIP_VALE3NXS(pVCpu, puValue);
            LogFlow(("iemCImplA64_sysp_TLBIP_VALE3NXS(%.16Rhxs) -> %Rrc\n", puValue, VBOXSTRICTRC_VAL(rcStrict)));
            return rcStrict;
        }
    }
    /* Fall back on handcoded handler. */
    return iemCImplA64_sysp_fallback(pVCpu, idSysReg, idxGprSrc, puValue);
}

/**
 * Implements the A64.SYSP instruction.
 *
 * @param   idSysReg    The system register to write (IPRT format).
 * @param   idxGprSrc   The source GPR register number (for exceptions).
 */
IEM_CIMPL_DEF_2(iemCImplA64_sysp, uint32_t, idSysReg, uint32_t, idxGprSrc)
{
    RTUINT128U const uValue =
    {
        {
            idxGprSrc     < ARMV8_A64_REG_XZR ? pVCpu->cpum.GstCtx.aGRegs[idxGprSrc].x     : 0,
            idxGprSrc + 1 < ARMV8_A64_REG_XZR ? pVCpu->cpum.GstCtx.aGRegs[idxGprSrc + 1].x : 0,
        }
    };
    return iemCImplA64_sysp_generic(pVCpu, idSysReg, idxGprSrc, &uValue);
}
